7/18/2014
CSC B58 midterm and solutions, Summer 2014
Mid-term test and sample solutions
2 July 2014
Note: The sequence of questions on your test was randomized. The following is one possible sequence.
1. [5 marks]
Consider the following circuit:
a) Write
7/18/2014
CSC B58 assignment two sample solution
Assignment two sample solution
This is just a sample! There are other possible valid answers, at least for the circuit design questions.
Question 1
I've already written about analyzing the list of stable st
Binary Conversion
Overview: Converting between
Binary and Decimal
Practice
Convert the following into decimal (unsigned)
0101b
1101011b
111111111b
Practice
Convert the following into binary
25d
573d
2047d
What about other bases?
Hexidecima
Lab 0
Lab rules
DE2 Boards
Dont need verilog yet
But you will for Lab 1
Pre-labs
Partners
Week 1 Review
Week 1 Review
Properties of electricity
Semiconductor materials
Doping (n-type and p-type)
p-n junctions
Transistors
Question
CSCB58 - Lab 1
Intro to Verilog
Learning Objectives
This lab will serve as an introduction to Verilog, and show you how to get Verligo code running on the DE2 board,
and use that code to manipulate switches and LEDs, as well as the 7-Segment displays.
Not
CSC 258H1 Y 2016 Midterm Test
Duration 1 hour and 50 minutes
Aids allowed: none
Last Name:
Student Number:
UTORid:
First Name:
Question 0.
[1 mark]
Read and follow all instructions on this page, and fill in all fields.
Do not turn this page until you have
CSCB58 - Lab 2
The case statement, Adders and ALUs
Learning Objectives
In this lab you will design (a) multiplexers using the case statement, (b) a simple ripple-carry adder, and (c) an
Arithmetic Logic Unit (ALU). You will also gain more practice with hi
CSCB58 - Lab 3
Latches, Flip-flops, and Registers
Learning Objectives
The purpose of this exercise is to investigate the fundamental synchronous logic elements: latches, flip-flops, and
registers.
Prelab
Part I (in-lab)
Part II (in-lab)
Clean work-space w
CSCB58 - Lab 0
Intro to The Lab & The DE2 Board
Learning Objectives
This week we will be getting you familiar with the lab and the boards that we will be using in later labs. You will
also learn how to use the Quartus software that is required in order to
CSCB58 - Lab 4
Clocks and Counters
Learning Objectives
The purpose of this lab is to learn how to create counters and to be able to control when operations occur when
the actual clock rate is much faster. We will also be looking at some features of Quartu
UNIVERSITY OF TORONTO
Faculty of Arts and Science
Summer 2016 Final Examination
CSC 258H1 Y
Duration 3 hours
Aids allowed: none
Last Name:
Student Number:
UTORid:
First Name:
Question 0.
[1 mark]
Read and follow all instructions on this page, and fill in
Week 5: Sequential
Circuits
Something to consider
Computer specs use terms
GB of RAM and
2.2GHz processors.
like 8
What do these terms mean?
RAM = Random Access Memory; 8GB = 8 billion ints
2.2 GHz = 2.2 billion clock pulses per se
The Verilog Primer
By Steve Engels
So you want to learn Verilog
Verilog is a new language that is used a lot in
the CSCB58 labs. Its not hard to learn, but it
is dierent from other languages that youve
seen before.
This primer is meant to give yo
Week 2:
Circuit Creation
You are here
Assembly Language
Processors
Arithmetic
Finite State
Logic Units
Machines
Devices
Flip-ops
Circuits
Gates
Transistors
#=
# Build by Altera University Program
#=
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE115F29C8
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignme
CSCB58:Computer
Organization
Instructor: Brian Harrington
[email protected]
* Original slides by Steve Engels
Why take CSCB58?
To better understand computers!
See what's going on "under the hood"
Open the black box, get rid of the myste
Week 3:
Logical Devices
Admin
Midterm
Monday June 26
2-4pm
IC130
Building up from gates
Some common and more complex structures:
Multiplexers (MUX)
Adders (half and full)
Subtractors
Comparators
Decoders
Seven-segment decoders
Mo
Week 2 Review
$#1$
! How&can&you&express&a&two?input&XOR&gate&as&a&
combination&of&NAND&and&NOT&gates?&
Week 2 Review
A
Question #1:
B
A
B
Y
Y
&express&a&two?input&XOR&gate&as&a&
Express XOR using only NAND and NOT gates
A
0
0
0
B
&of&NAND&and&NOT&g
Week 5 Review
Question #1
R
Q
Complete the truth table
S
S
R
QT
QT
QT+1
QT+1
0
0
0
1
0
1
0
0
1
0
1
0
0
1
X
X
0
1
Reset
1
0
X
X
1
0
Set
1
1
X
X
0
0
Forbidden
Hold
Q
Question #2
S
What are the output
C
values from Q and Q
given the followin
Week 3 Review
Question)#1)
Question #1
a) How&do&you&write&the&number&78&as&an&85bit&
binary&number?&
How do you write 78 as an 8 bit binary number?
128 64 32 16
0
1
0
0
8
4
2
1
1
1
1
0
b) What&is&the&twos&complement&of&01101101?&
What is 11011001b i
7/18/2014
CSC B58 tutorial eight
CSC B58 tutorial eight, week of July 14
First, we went thorugh the "standard instruction fetch sequence" a bit:
0 P_u,MRi,Ra,Zr A StCryI,Ad Zi
. Cot A_n ed eo , e ar-n d, _n
1 Zot P_n Wi MC
. _u, Ci, at F
2 MRot I_n
. D_u,
Then went through the boolean algebra laws handout (see http:/mathlab.utsc.utoronto.ca/courses/cscb58s14/boollaws.pdf ).
Then proved the three absorption laws (see http:/mathlab.utsc.utoronto.ca/courses/cscb58s14/notes/absorption-proofs.html ).
7/18/2014
CSC B58 tutorial two
CSC B58 tutorial two, week of May 19
There is a TA office hour leading up to the assignment due date; please see the course web page. And you can always send questions to ajr by e-mail.
Here are some administrative details r
7/18/2014
CSC B58 Assignment 1 solutions, Summer 2014
CSC B58 Assignment 1 solutions, Summer 2014
1.
1a.
1b.
1c. F(0,1,0,1)
1d.
2.
Note: you didn't have to include as much "justification" as I have put here, if it was obvious how you were getting from one
Sequential Circuits SR Latch:
s _
0 Q
R . Q
vxv
SR Latch: SR Latch:
8 i a S , a
S R Q Q S R Q Q
0 1 0 I 0 1 0 I
1 0
WW} SR Latch:
SR Latch:
_Q
SR Latch:
SR Latch:
_Q Clocked SR Latch:
Why Clock?
' smooth transitions
Ideal: ft; l
Ogle I
Multi-word addition
To do multi-word addition, use the carry-out bit.
Add from lowest word to the left.
Example with four-bit words:
00110101 + 00011100 (53 + 28)
0 High word of X is 0011
O Low word of x is 0101
0 High word of y is 0001
0 Low word