ECE 210 Introduction to Digital Logic Design
Lab 2 Combinational Logic Design
Fall Term 2014 University Of Alberta
INTRODUCTION
In this lab, you will implement combinatorial logic circuits using the Xilinx FPGA
development board. The lab contains two part
1. (5 pts) Simplify the following Boolean expression:
(X+Y)(X+Z)ZY + X(Y+Z) + (ZYX+Y)(ZYX+XZ)
The answer should be X(Y+Z). Note that they are several ways to perform
simplification. Show all steps of the simplification process.
a.
(1.5 pt) Perform simplif
ECE 210 Introduction to Digital Logic Design
Lab 4 Finite State Machines
Fall Term 2014 University Of Alberta
INTRODUCTION
Logic circuits are classified into two types, combinational and sequential. A
combinational circuit is one whose outputs depend only
9/29/2010
ECE/
UoA
ECE
210
EE 280
Introduction to Digital Logic Design
12. NANDNAND and NORNOR Networks
EE280 Lecture 12
12  1
NAND Gates
 read Chapter 7.3
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ECE 210
Tutorial #1
1.Given is the following Boolean function
F(A, B, C, D) = A B + (C D) +CAB + ABC
where the operation is defined as follows
a
0
0
1
1
(a)
(a)
b
0
1
0
1
ab
1
0
1
0
Simplify F algebraically
Determine the dual and complement of this simpli
ECE 210
Tutorial #2
1. Implement a full adder circuit using one 8to1 MUX for the sum output and one 4to1 MUX for the cout (output carry). For the 8to1 MUX you must connect a, b, and cin
(input carry) to the control inputs, and 0 and 1 values to the M
ECE 210 Section A3
Tutorial
1.Given is the following Boolean function
F(A, B, C, D) = A B + (C D) +CAB + ABC
where the operation is defined as follows
a
0
0
1
1
(a)
(a)
b
0
1
0
1
ab
1
0
1
0
Simplify F algebraically.
Determine the dual and complement of th
TUTORIAL #2
SOLUTIONS
1. Implement a full adder circuit using one 8to1 MUX for the sum output and one 4to1 MUX for the cout (output carry). For the 8to1 MUX you must connect a, b, and
cin (input carry) to the control inputs, and 0 and 1 values to the
ECE 210 A3
TUTORIAL
December 6, 2015
1. Design a counter, which realizes the following sequences depending on the value of
the control signal S:
if S =0 then the sequence is 0320
if S =1 then the sequence is 3023.
Use positive edge triggered T f
AC STEADYSTATE ANALYSIS
LEARNING GOALS
SINUSOIDS
Review basic facts about sinusoidal signals
SINUSOIDAL AND COMPLEX FORCING FUNCTIONS
Behavior of circuits with sinusoidal independent sources
and modeling of sinusoids in terms of complex exponentials
PHAS
ECE 210
Introduction to Digital Logic Design
Lecture 20.
Complements: Twos and Ones
ECE 210 Lecture 20
20  1
Number Representation
 Read Chapter 1.5, 2.1, and 2.2 for next class
Negative Numbers
How do we represent negative numbers in a word length of n
ECE 210
Introduction to Digital Logic Design
Lecture 21.
Binary Adders
ECE 210 Lecture 22
21  1
Binary Adders
Binary Addition
General Adder
Each open arrow represents multiple variables, in this case binary numbers
If each number has n bits, each arrow r
ECE 210
Introduction to Digital Logic Design
Lecture 19.
MultiLevel NAND and NOR Networks
ECE 210 Lecture 19
19  1
MultiLevel NAND and NOR Networks
Similar to design of twolevel networks
simplify the expression
design a multilevel network of OR & A
ECE 210
Introduction to Digital Logic Design
Lecture 17.
Multiplexers and Decoders
ECE 210 Lecture 17
17  1
Logic Functions Realized with MUX
4to1 MUX can realize any 3variable function
8to1 MUX can realize a 4 variable function
2nto1 MUX can real
ECE 210
Introduction to Digital Logic Design
Lecture 22.
ReadOnly Memories & Programmable Logic Arrays
ECE 210 Lecture 22
22  1
ReadOnly Memories
Memory is like an array of mailboxes (registries of binary data)
A stored array of binary data which can b
ECE/UA
10/5/2010
ECE 210
EE 280
Introduction to Digital Logic Design
15. Multiplexers
EE280 Lecture 15
15  1
Integrated Circuits Types
IC can be classified into:
smallscale integration (SSI)
NAND, MOR, AND, OR gates, inverters, flipflops
SSI package u
ECE 210 INTRODUCTION TO DIGITAL ELECTRONICS
ASSIGNMENT # 8
10 pts total
Due Monday, November 16, 2015 at 3:00 PM
(return to the appropriate sections box 2nd floor ECERF building)
_
1 (3 points) Using the PLA shown below, implement the following 4input, 3
ECE 210
Introduction to Digital Logic Design
2. Number Systems and Conversion
U of A
21
Number Systems and Conversion
Decimal system:  most commonly used number system
 uses10 different symbols
0 1 2 3 4 5 6 7 8 9
But, does this mean that we can only
ECE 210 (section A1) INTRODUCTION TO DIGITAL LOGIC DESIGN
ASSIGNMENT # 1
10 pts total
Due September 19 (R), 2013 at 5:00pm
(return to the appropriate sections box near entrance to ECE offices)
_
1. (3 pts) Convert 11010110001.0112
a. to octal and to hexad
ECE 210 (section A1) INTRODUCTION TO DIGITAL LOGIC DESIGN
ASSIGNMENT # 2
10 pts total
Due September 26 (R), 2013 at 5:00pm
(return to the appropriate sections box near entrance to ECE offices)
_
1. (a) Using Boolean theorems and laws show that the Boolean
ECE 210 (A1, A3)
Design examples (combinational circuits)
A design process typically involves the five steps discussed in class. Execute each step for the following
problems.
(1) Design a combinational circuit with three inputs (x, y, z) and one output (F
ECE 210 INTRODUCTION TO DIGITAL ELECTRONICS
ASSIGNMENT # 4
10 pts total
Due Tuesday, October 13, 2015 at 3:00 PM
(return to the appropriate sections box 2nd floor ECERF building)
_
Problem 1 (2 pts) Maxterms and minterms realization of logic networks.
a)
ECE 210 INTRODUCTION TO DIGITAL ELECTRONICS
ASSIGNMENT # 6
10 pts total
Due Monday, October 26, 2015 at 3:00 PM
(return to the appropriate sections box 2nd floor ECERF building)
_
1. [2 points] Implement a Boolean function F(A, B, C, D) shown below using
ECE 210 INTRODUCTION TO DIGITAL ELECTRONICS
ASSIGNMENT # 2
10 pts total
Due Monday, September 28, 2015 at 3:00 PM
(return to the appropriate sections box 2nd floor ECERF building)
_
1. (1 point) Design the 4321 weighted code for decimal digits. Is it poss
ECE 210 INTRODUCTION TO DIGITAL ELECTRONICS
ASSIGNMENT # 3
10 pts total
Due Monday, October 5, 2015 at 3:00 PM
(return to the appropriate sections box 2nd floor ECERF building)
_
Problem 1 (1 point) Determine the minterm representation for the circuit sho
ECE 210 INTRODUCTION TO DIGITAL ELECTRONICS
ASSIGNMENT # 5
10 pts total
Due Monday, October 19, 2015 at 3:00 PM
(return to the appropriate sections box 2nd floor ECERF building)
_
1. (2 points) The 5421 weighted code is provided below
Decimal
0
1
2
3
4
ECE 210 INTRODUCTION TO DIGITAL ELECTRONICS
ASSIGNMENT # 10
10 pts total
Due Monday, December 7, 2015 at 3:00 PM
(return to the appropriate sections box 2nd floor ECERF building)
_
1 (2 points) A Johnson counter is shown below
D
A
D
A
B
D
B
C
D
C
D
D
cloc
ECE 210 INTRODUCTION TO DIGITAL ELECTRONICS
ASSIGNMENT # 9
10 pts total
Due Monday, November 23, 2015 at 3:00 PM
(return to the appropriate sections box 2nd floor ECERF building)
1 (2 points) Design a sequential circuit using rising edge triggered Tflip
ECE 210 INTRODUCTION TO DIGITAL ELECTRONICS
ASSIGNMENT # 1
10 pts total
Due Monday, September 21, 2015 at 3:00 PM
(return to the appropriate sections box 2nd floor ECERF building)
_
1. (3 pts) Convert the following numbers from the given base to the other
STEADYSTATE POWER ANALYSIS
LEARNING GOALS
Instantaneous Power
For the special case of steady state sinusoidal signals
Average Power
Power absorbed or supplied during one cycle
Maximum Average Power Transfer
When the circuit is in sinusoidal steady state
MAGNETICALLY COUPLED NETWORKS
LEARNING GOALS
Mutual Inductance
Behavior of inductors sharing a common magnetic field
Energy Analysis
Used to establish relationship between mutual reluctance and
selfinductance
The ideal transformer
Device modeling compone
CAPACITANCE AND INDUCTANCE
Introduces two passive, energy storing devices: Capacitors and Inductors
LEARNING GOALS
CAPACITORS
Store energy in their electric field (electrostatic energy)
Model as circuit element
INDUCTORS
Store energy in their magnetic fie
NODAL AND LOOP ANALYSIS TECHNIQUES
LEARNING GOALS
NODAL ANALYSIS
LOOP ANALYSIS
Develop systematic techniques to determine all the voltages
and currents in a circuit
NODE ANALYSIS
One of the systematic ways to
determine every voltage and
current in a circ
LOOP ANALYSIS
The second systematic technique
to determine all currents and
voltages in a circuit
IT IS DUAL TO NODE ANALYSIS  IT FIRST DETERMINES ALL CURRENTS IN A CIRCUIT
AND THEN IT USES OHMS LAW TO COMPUTE NECESSARY VOLTAGES
THERE ARE SITUATION WHERE