EE 280
Introduction to Digital Logic Design
Lecture 1.
Introduction
EE280 Lecture 1
11
EE 280 Introduction to Digital Logic Design
Instructors:
Dr. Lukasz Kurgan (section A1)
office: ECERF 6th floor,
EE 280
Introduction to Digital Logic Design
Lecture 10.
Word Problems
Word Problems
 Read Chapter 4.3, 4.4, and 4.5 for next class
Conversion of Sentences to Equations
Procedure:
 Represent phrases
EE 280
Introduction to Digital Logic Design
Lecture 14.
Multilevel Gate Networks
EE280 Lecture 14
14  1
MultiLevel Gate Networks
A Boolean function may be transformed from an algebraic expression i
EE 280
Introduction to Digital Logic Design
Lecture 2.
Number Systems and Conversion
EE280  Lecture 2
1
Number Systems and Conversion
 Read Chapter 1.4 for next class (Complements)
Decimal system: 
EE 280
Introduction to Digital Logic Design
Lecture 3.
Complements: Twos and Ones
EE280 Lecture 3
31
Number Representation
 Read Chapter 1.5, 2.1, and 2.2 for next class
Negative Numbers
How do we r
EE 280
Introduction to Digital Logic Design
Lecture 25.
Latches and FlipFlops
EE280 Lecture 25
25  1
Enabled or Clocked SR Latch
A more sophisticated flipflop
an input is effective only when enab
EE 280
Introduction to Digital Logic Design
Lecture 32.
Redundant States
EE280 Lecture 32
32  1
Redundant States
Given description of a sequential circuit we usually first derive a state table
for p
EE 280
Introduction to Digital Logic Design
Lecture 4.
Binary Codes and Boolean Operations
EE280 Lecture 4
41
Binary Codes
read Chapter 2.2, 2.4, and 2.5 for next class
Computers and other digital sy
EE 280
Introduction to Digital Logic Design
Lecture 9.
Logic Families and Their Characteristics
Logic Families
TTL  TransistorTransistor Logic
standard logic family; used for the longest time.
ECL
EE 280
Introduction to Digital Logic Design
Lecture 27.
Registers
EE280 Lecture 27
27  1
Registers
A register is a group of latches or FlipFlops (FFs) that are used as a single unit
to store a group
EE 280
Introduction to Digital Logic Design
Lecture 22.
Binary Adders
EE280 Lecture 22
22  1
Binary Adders
Binary Addition
General Adder
Each open arrow represents multiple variables, in this case bi
EE 280
Introduction to Digital Logic Design
Lecture 18.
MultiLevel NAND and NOR Networks
EE280 Lecture 18
18  1
MultiLevel NAND and NOR Networks
Similar to design of twolevel networks
simplify th
EE 280 INTRODUCTION TO DIGITAL ELECTRONICS
ASSIGNMENT # 7
10 pts total
Because of the holidays the assignment is due at 3:00PM Wednesday, November 12, 2008
(return to the appropriate sections box near
EE 280 INTRODUCTION TO DIGITAL ELECTRONICS
ASSIGNMENT # 4
10 pts total
Due October 14, 2008 at 3:00PM
(return to the appropriate sections box near entrance to ECE offices)
_
Question 1 (2pts) Minimiza
EE 280
Introduction to Digital Logic Design
Lecture 24.
Latches and FlipFlops
EE280 Lecture 24
24  1
Combinatorial and Sequential Networks
Combinational: Output values depend only on present input v
EE 280 INTRODUCTION TO DIGITAL ELECTRONICS
ASSIGNMENT # 10
10 pts total
Due date: Monday, December 1, 2008 at 3:00pm
(return to the appropriate sections box near entrance to ECE offices)
_
1. [3 point
EE 280
Introduction to Digital Logic Design
Lecture 28.
Design of Sequential Networks
EE280 Lecture 28
28  1
Sequential Circuits
In sequential circuit the sequence of outputs and FF states generally
EE 280
Introduction to Digital Logic Design
Lecture 23.
ReadOnly Memories & Programmable Logic Arrays
EE280 Lecture 23
23  1
ReadOnly Memories
Memory is like an array of mailboxes (registries of bi
EE 280 INTRODUCTION TO DIGITAL ELECTRONICS
ASSIGNMENT # 6
(10 pts TOTAL)
Due 3:00 pm, November 3, 2008
(return to the appropriate sections box near entrance to ECE offices)
_
1. [2 points] Implement a
EE 280 INTRODUCTION TO DIGITAL ELECTRONICS
ASSIGNMENT # 8
(10 pts TOTAL)
Due 3:00 pm, November 17, 2008
(return to the appropriate sections box near entrance to ECE offices)
_
1. (2 pts) Derive the tr
EE 280
Introduction to Digital Logic Design
Lecture 8.
Positive/Negative Logic and Diode Gates
Positive & Negative Logic

Consider a logic gate realized electronically
Each I/P and O/P will have one
EE 280
Introduction to Digital Logic Design
Lecture 30.
Multiple Inputs and Outputs
EE280 Lecture 30
30  1
Multiple Inputs and Outputs
A given sequential circuit may have multiple inputs and outputs
EE 280
Introduction to Digital Logic Design
Lecture 21.
Multiplexers and Decoders
EE280 Lecture 21
21  1
Logic Functions Realized with MUX
4to1 MUX can realize any 3variable function
8to1 MUX ca
EE 280
Introduction to Digital Logic Design
Lecture 6.
Simplification Theorems and Laws
MultiInput Gates
So far, we have only considered 2input gates.
In practice, can have more than 2 inputs.
i.e.
EE 280 INTRODUCTION TO DIGITAL ELECTRONICS
ASSIGNMENT # 5
10 pts total
Due October 27, 2008 at 3:00pm
the deadline is moved by one week due to the midterms
(return to the appropriate sections box near
EE 280
Introduction to Digital Logic Design
Lecture 16.
General Two Level Design
EE280 Lecture 16
16  1
General Two Level Design
A twolevel network of AND & OR gates can be converted to NAND &
NOR
EE 280
Introduction to Digital Logic Design
Lecture 13.
Karnaugh Maps
Incompletely Specified Functions and Karnaugh Maps
e.g. F = m (1, 3, 5, 7, 9) + d(6, 12, 13)
plot
for each m
for each d, thus:
AB
EE 280 INTRODUCTION TO DIGITAL ELECTRONICS
ASSIGNMENT # 9
10 pts total
Due date: Monday, November 24, 2006 at 3:00pm
(return to the appropriate sections box near entrance to ECE offices)
_
1. [3 point
EE 280
Introduction to Digital Logic Design
Lecture 11.
Minterms and Maxterms
Minterm and Maxterm Expressions
 Read Chapter 5.1, 5.2, and 5.3 for next class
Definition: a minterm of n variables is a
EE 280 INTRODUCTION TO DIGITAL ELECTRONICS
ASSIGNMENT # 2
10 pts total
Due September 29, 2008 at 3:00pm
(return to the appropriate sections box near entrance to ECE offices)
_
1. (1 pt) Add ( 910) + (