EECE-315 Prelab 13 1. Refer to the circuit shown in Fig. 1. The output current is the current leaves the collector. Calculate the open-loop and closed-loop transconductance midband gains. Also calculate the lower 3 dB cutoff frequencies with the feedback
EECE-315 Prelab 11 In this lab, you will be verifying the JFET bias design that you did in the homework problem. 1. Check back to the homework problem and record the values of all components used in the bias circuits, including the supply voltage. 2. Also
EECE-315 Prelab 10 1. Assume = 120. Calculate ICQ and the midband voltage gain for the circuit shown below. 2. Calculate the corner frequency due to each capacitor individually using the shortcircuit time constant method. What is the estimated lower -3 dB
EECE-315 Prelab 9 1. Refer back to your BJT amplifier homework problem and collect the following information: a. The values of all resistors used in the circuit, as well as the value of VCC. b. Your design values of ICQ. c. Your design values of voltage g
EECE-315 Prelab 8 1. Devise a technique (NOT using a curve tracer) to measure VP of a JFET. Show your circuit and explain how you do it.
2. Devise a technique to measure IDSS of a JFET. Show your circuit and explain how you do it. 3. Find data sheets of t
EECE-315 Prelab 7 Assume = 150. Analyze all circuits shown in Fig. 1, Fig. 2 and Fig. 3 of Lab-7. (a) Derive ICQ and VCEQ. Verify the transistor is biased in its active region. (b) Assume all capacitors have infinite capacitances. Derive the (ac) voltage
EECE-315 Prelab 6 In this lab, you will be verifying the BJT bias design that you did in homework problem. 1. Check back to homework problems and record the values of all components used in the bias circuit, including the supply voltage. 2. Also record th
EECE-315 Prelab 5 1. Assuming = 100, design a bias circuit to give a nominal ICQ = 2 mA with a supply voltage of 12 V. Assume the BJT is biased in its active region and the emitter resistance is 2.2 k. Use 5% tolerance resistors. 2. Calculate the largest
EECE 315 Prelab 4
Assume = 100, VBE(active) = 0.7 V, VBE(sat) = 0.75 V, and VCE(sat) = 0.2 V. 1. Calculate ICQ and VCEQ for parts 1, 3 and 4 given in Lab 4. 2. Determine ICQ and RC for part 5 given in Lab 4.
EECE 315 Lab 4 1. Let R1 = 4.7 k , R2 = 1 k . C
EECE-315 Prelab 3 In this lab you will be determining the performance of a Zener diode (1N4735) voltage regulator shown in Lab 3. Assume R = 50 . 1. Devise a method to measure Vzo and the Zener resistance, rz of a Zener diode. Show schematics for the appa
EECE-315 Prelab 2 Assume V =0.6 V for all diodes, and assume the zener diode is ideal (rz = 0, V.= 0.6 V). (a) Analyze circuits given in Fig. 1, Fig. 2, Fig. 3 and Fig. 6 of Lab 2, and then plot the input and output voltage waveforms. (b) Use PSPICE to pl
EECE-315 Prelab 1 1. On a piece of four cycle semilog paper, plot the equation y = 106 e30x for x = 0.1, 0.15, 0.20, 0.25, 0.30. 2. Bring to lab a clean piece of 4 cycle semilog paper. 3. In lab 1 you will be taking i-v measurements on a forward-biased di