KING FAHD UNIVERSITY OF PETROLEUM & MINERALS
COLLEGE OF COMPUTER SCIENCES & ENGINEERING
COMPUTER ENGINEERING DEPARTMENT
COE 405 Design and Modeling of Digital Systems
Syllabus - Term 062
Catalog Description
Design methodology. Hardware modeling basics. Mo

Name: KEY
Id#
COE 405, Term 062
Design & Modeling of Digital Systems
Quiz# 3
Date: Saturday, April 21, 2007
Q.1.
(i) Your are required to model the function - to compute the 2s complement of a
Bit_Vector operand. You are required to model the function wit

COE 405
Design & Modeling of Digital Systems
Course Project
Simple CPU Design & Modeling
Due on: Wednesday May 30, 2007
In this project, you are required to design and model a simple Central Processing Unit
(CPU) interfaced with memory. You need to design

s Another Package Example
Package Body Basic_Utilities IS
Function fgl (w, x, gl: BIT) Return BIT IS
Begin
Return (w AND gl) OR (NOT x AND gl) OR (w AND NOT x);
End fgl;
Function feq (w, x, eq: BIT) Return BIT IS
Begin
Return (w AND x AND eq) OR (NOT w AN

s Subprograms
s Subprograms consist of functions and procedures.
s Subprograms are used to
Simplify coding,
Achieve modularity,
Improve readability.
s Functions return values and cannot alter values of their parameters.
s Procedures used as a statement an

s VHDL Terms
s Entity:
All designs are expressed in terms of entities
Basic building block in a design
s Ports:
Provide the mechanism for a device to communication with its environment
Define the names, types, directions, and possible default values for

VHDL OBJECT : Something that can hold a value of a given Data Type.
VHDL has 3 classes of objects
CONSTANTS
VARIABLES
SIGNALS
Every object & expression must unambiguously belong to one named Data Type
Every object must be Declared.
VHDL Object
VHDL Obj

s Package IEEE.Std_Logic_1164
Package Std_Logic_1164 IS
- logic state system (unresolved)
Type Std_Ulogic IS
( U,
X,
0,
- Uninitialized
cfw_Important For Sequential Systems
- Forcing Unknown cfw_Contention
- Forcing 0
1,
Z,
- Forcing 1
- High Impedance
W

s Interface and Architectural Specifications
s Packages
s Packages are used to encapsulate information that is to be shared among multiple
design units.
s A package is used by the USE clause
e.g. Use work.package_name.all
s Package Examples
s Standard Pac

s Design Files
s Design file is a sequence of
Lexical Elements
Separators
s Separators
Any # of separators allowed between lexical elements
Space character
Tab
Line Feed / Carriage Return (EOL)
s Lexical Elements:
Delimiters `meaningful separator characte

s Basic Components & Graphical Notation
s Three basic components are used
s Will use as the basic components of several designs
s A graphical notation helps clarify wiring
s Entity Syntax
s A Cascadable Single-Bit Comparator
s When a > b the a_gt_b become

s Executing a Procedure
s Actual parameters are evaluated.
s Actuals are associated with their formals.
s Sequential statements are executed in order.
s Procedure exits when
End of the procedure is reached
A return statement is executed; no value allowed

Name: KEY
Id#
COE 405, Term 062
Design & Modeling of Digital Systems
Quiz# 2
Date: Monday, March 26, 2007
Q.1.
Given the following signal assignments, show all transactions placed on each signal. At
each event, show transactions that are appended, overwri

Name: KEY
Id#
COE 405, Term 062
Design & Modeling of Digital Systems
Quiz# 1
Date: Saturday, March 17, 2007
Q.1. It is required to model a 4-bit comparator that compares two 4-bit numbers A=A3A2A1A0
and B=B3B2B1B0, and produces two outputs GT and LT. If A

Name:
Id#
COE 405, Term 062
Design & Modeling of Digital Systems
Quiz# 3
Date: Saturday, April 21, 2007
Q.1.
(i) Your are required to model the function - to compute the 2s complement of a
Bit_Vector operand. You are required to model the function without

KING FAHD UNIVERSITY OF PETROLEUM & MINERALS
COMPUTER ENGINEERING DEPARTMENT
COE 405 Design and Modeling of Digital Systems
Term 062 Lecture Breakdown
Lec#
Date
Topics
Ref.
1
S 17/2
Ch. 1
2
M 19/2
3
W 21/2
4
S 24/2
5
M 26/2
6
W 28/2
7
S 3/3
8
M 5/3
9
W 27

COE 405, Term 062
Design & Modeling of Digital Systems
HW# 1
Due date: Wednesday, March. 14
Q.1.
Consider the 4-bit carry-look-ahead adder (CLA) block shown below:
A3-A0
C3
B3-B0
4-bit CLA
Cin
S3-S0
(i) Describe an Entity CLA4 in VHDL for this 4-bit CLA u

COE 405, Term 062
Design & Modeling of Digital Systems
HW# 2
Due date: Monday, March 26, 2007
Q.1.
It is required to design an 8-bit shift register. The shift register should be able to
shift or rotate either left or right based on the following table:
S1

COE 405, Term 062
Design & Modeling of Digital Systems
HW# 3
Due date: Monday, April 16, 2007
Q.1.
You are required to model an ALU that has the following entity description:
Entity ALU is
Generic (N: Natural :=4);
Port (A, B: IN Bit_Vector(N-1 Downto 0);

COE 405, Term 062
Design & Modeling of Digital Systems
HW# 4
Due date: Saturday, May12, 2007
Q.1.
It is required to model an N-bit Serial Multiplier. The VHDL Entity description of the
n-bit multiplier is given below:
Entity multiplier is
Generic (n: Posi

COE 405, Term 062
Design & Modeling of Digital Systems
HW# 1 Solution
Due date: Wednesday, March. 14
Q.1.
Consider the 4-bit carry-look-ahead adder (CLA) block shown below:
A3-A0
C3
B3-B0
4-bit CLA
Cin
S3-S0
(i) Describe an Entity CLA4 in VHDL for this 4-

COE 405, Term 062
Design & Modeling of Digital Systems
HW# 2 Solution
Due date: Monday, March 26, 2007
Q.1.
It is required to design an 8-bit shift register. The shift register should be able to
shift or rotate either left or right based on the following

COE 405, Term 062
Design & Modeling of Digital Systems
HW# 3 Solution
Due date: Monday, April 16, 2007
Q.1.
You are required to model an ALU that has the following entity description:
Entity ALU is
Generic (N: Natural :=4);
Port (A, B: IN Bit_Vector(N-1 D

COE 405, Term 062
Design & Modeling of Digital Systems
HW# 4 Solution
Due date: Saturday, May12, 2007
Q.1.
It is required to model an N-bit Serial Multiplier. The VHDL Entity description of the
n-bit multiplier is given below:
Entity multiplier is
Generic

Name:
Id#
COE 405, Term 062
Design & Modeling of Digital Systems
Quiz# 1
Date: Saturday, March 17, 2007
Q.1. It is required to model a 4-bit comparator that compares two 4-bit numbers A=A3A2A1A0
and B=B3B2B1B0, and produces two outputs GT and LT. If A>B,

Name:
Id#
COE 405, Term 062
Design & Modeling of Digital Systems
Quiz# 2
Date: Monday, March 26, 2007
Q.1.
Given the following signal assignments, show all transactions placed on each signal. At
each event, show transactions that are appended, overwritten

s Digital System Design
s Realization of a specification subject to the optimization of
Area (Chip, PCB)
Increase manufacturing yield
Lower manufacturing cost
Reduce packaging cost
Performance
Propagation delay (combinational circuits)
Cycle time and late