University of Victoria
Department of Computer Science
CSC 355 Digital Logic and Computer Design
ASSIGNMENT 1
DUE Thursday September 24 AT BEGINNING OF CLASS
Neatness Counts!
It is expected that answers to assignments are either typed or written *extremely
Instructor: J.C. Muzio
Section: S01
UNIVERSITY OF VICTORIA
E XAMINATIONS APRIL 1997
C OMPUTER SCIENCE 355 S01
DURATION: 3 Hours
INSTRUCTOR: Jon C. Muzio
No. of pages: 5 + cover
TO BE ANSWERED IN EXAMINATION BOOKLETS
STUDENTS MUST COUNT THE NUMBER OF PAGES
a canonical, normal, or standard
form of a mathematical object is a
standard way of presenting that
object as a mathematical
expression.
The distinction between
"canonical" and "normal"
forms varies by subfield. In
most fields, a canonical form
specifies
Binary data is data whose unit can
take on only two possible states,
traditionally termed 0 and +1 in
accordance with the binary
numeral system and Boolean
algebra.
Boolean algebra is the subarea
of algebra in which the values
of the variables are the tru
CSC 355 Midterm sample questions:
QUESTION 1
[10 marks total]
(a) Draw a logic diagram (circuit) for the function f(A, B, C, D) = (A + B)(C + D'),
using only 2-input NOR gates ( inverted inputs are available).
(b) Design a 2-input, 1-bit wide multiplexer
.include "m2560def.inc"
.cseg
ldi ZH,high(init<1)
; initialize Z to point to init
ldi ZL,low(init<1)
lpm r0,Z
; get the first byte and increment Z
sts value,r0
; store into A
;*-1 Do not change anything above this line to the -*
;*
body:
foo:
ldi
ldi
lds
University of Victoria
Department of Computer Science
CSC 355 Digital Logic and Computer Design
Lab 3: Multiplexer & Adder Circuits
Introduction
The goal of this lab is for you to prepare the design of the combinational circuits that will be implemented o
University of Victoria
Department of Computer Science
CSC 355 Digital Logic and Computer Design
Lab 2: Karnaugh Map Simplification & 2-input NAND Circuits
Introduction
The goal of this lab is for you to prepare the design of the combinational circuits tha
University of Victoria
Department of Computer Science
CSC 355 Digital Logic and Computer Design
Lab 1: Introduction to Logic Gates and Design Works [15]
Introduction
Welcome to the 355 Labs. The labs have been designed to give you a rewarding learning exp
University of Victoria
Department of Computer Science
CSC 355 Digital Logic and Computer Design
ASSIGNMENT 2 DUE Thursday October 14, 2015 AT BEGINNING OF CLASS
Neatness Counts!
It is expected that answers to assignments are either typed or written *extre
University of Victoria
Department of Computer Science
CSC 355 Digital Logic and Computer Design
ASSIGNMENT 1
DUE Thursday September 24 AT BEGINNING OF CLASS
Neatness Counts!
It is expected that answers to assignments are either typed or written *extremely
STUDENTNAMEANDNUMBER:
CSC355Assignment2Fall2014
Totalmarks=50.Dueat2p.m.onWednesday,Nov.5,2014
Question1[6marks]
ConsiderthefollowingVHDLprocess.AandBareinputportsoftypeinteger,andToutisanoutputportof
typeinteger.
ARCHITECTURE test2 IS
SIGNAL T1,T2 : inte
COMPUTER SCIENCE 355 FALL 2012
Pre-lab: Specifications and Requirements
For all of the labs after the first one, the pre-lab is required to be submitted by 1:30 p.m. on
the Monday of the lab week.
The pre-lab should be in a form that is easily marked by t
COMPUTER SCIENCE 355
FALL 2013
ASSIGNMENT 2 DUE Thursday Nov 7 AT BEGINNING OF CLASS
The assignment is marked out of 100
For any design problems, use a Mealy machine
1. [10 marks]. Start with the NAND circuit for a master slave trailing edge J-K flip-flop
Karnaugh Maps: Examples
Simplify a Function
Design a Code Converter
Incompletely Specified Functions
Dont Care States
SOP: 5 variable K Map
POS Example: Grouping 0s
Given a POS, draw the K-map, then give minimal SOP
1
Simplify a Function
Simplify t
K ARNAUGH M APS
K ARNAUGH M APS
K-Map is a method to simplify Boolean algebra expressions.
The K-map reduces the need for extensive calculations by taking
advantage of humans' pattern-recognition capability, permitting the
rapid identification and elimi
ASSIGNMENT #3
Due November 21, 2011 @ 5:00 PM
Late assignments will not be marked and will get 0 credits.
Students are responsible for putting their assignments in the
correct drop box. If any assignment is found in the wrong
drop box, it will not be mark
Instructor: J.C. Muzio
Section: F01
UNIVERSITY OF VICTORIA
E XAMINATIONS DECEMBER 1997
C OMPUTER SCIENCE 355 F01
DURATION: 3 Hours
INSTRUCTOR: Jon C. Muzio
No. of pages: 5 + cover
TO BE ANSWERED IN EXAMINATION BOOKLETS
STUDENTS MUST COUNT THE NUMBER OF PA
Assignment #2 Solutions
1. Construct a 16 x 1 multiplexer with two 8 x 1 and one 2 x 1 multiplexers. Use block
diagrams.
2. Implement the following four Boolean expressions simultaneously in one logic circuit using
ONLY three half adders.
a) D = A B C
b)