Introduction to Logic Design
EEE-248/CNG232
Lecture Notes
Dr. Ali Muhtarolu
Spring 2011
METU Northern Cyprus Campus
Introduction
Lecture 1
Ali Muhtarolu
2
Sample Custom Digital IC Design Flow
Architecture
Design &
Verification
Ali Muhtarolu
Logic
Design &
Introduction to Logic Design
EEE-248/CNG232
Lecture Notes
Dr. Ali Muhtarolu
Spring 2011
METU Northern Cyprus Campus
References:
Main Textbook:
Mano & Ciletti, Digital Design (4th Ed.), Prentice Hall, 2007
Auxiliary Textbooks: Wakerly, Digital Design Princ
Introduction to Logic Design
EEE-248/CNG232
Lecture Notes
Dr. Ali Muhtarolu
Spring 2011
METU Northern Cyprus Campus
References:
Main Textbook:
Mano & Ciletti, Digital Design (4th Ed.), Prentice Hall, 2007
Auxiliary Textbooks: Wakerly, Digital Design Princ
EXPERIMENT #6
FSM DESIGN FOR CALCULATOR CONTROL
6.1 OBJECTIVE
Altera toolset will be used in Experiments 6 & 7 to build a 4-bit calculator. Only the Finite State
Machine (FSM) that forms the backbone of the calculator controller will be implemented in thi
EXPERIMENT #7: FINAL PROJECT
4-BIT CALCULATOR DESIGN, SIMULATION, and IMPLEMENTATION
7.1 OBJECTIVE
A datapath will be added to the calculator controller designed in Experiment 6. The FSM from
the last experiment will be enhanced to deliver the control sig
EXPERIMENT #5
COMBINATIONAL AND SEQUENTIAL DESIGN
USING STANDARD COMPONENTS
5.1 OBJECTIVE
The objective of this experiment is to get hands-on experience with wiring/building
combinational and sequential digital circuits using standard SSI (Small Scale Int
EXPERIMENT #2 & #3
HIERARCHICAL DESCRIPTION OF COMBINATIONAL LOGIC
(ADDERS, DECODERS, MULTIPLEXERS) WITH MULTIBIT SIGNALS
2.1 OBJECTIVE
This laboratory exercise will build on the design entry knowledge acquired in the first lab to design
more advanced com
EXPERIMENT #4
SYNCHRONOUS BUILDING BLOCKS
4.1 OBJECTIVE
Simple synchronous storage elements with reset, load, and shift functions will be studied in this
experiment. These will then be used to build a 2-bit shift register with reset, and load capability.
METU NORTHERN CYPRUS CAMPUS
Logic Design
EEE248/CNG 232 LABORATORIES
Spring 2011
Regulations:
Students are not permitted to perform an experiment without doing the preliminary work before
coming to the laboratory. It is not allowed to do the preliminary w
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decode is
Port ( s : in STD_LOGIC_VECTOR (4 downto 0);
cout : out STD_LOGIC_VECTOR (7 downto 0);
end decode;
architecture Behavioral of deco
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity add4bit is
Port ( cin : in STD_LOGIC;
x : in STD_LOGIC_VECTOR (3 downto 0);
y : in STD_LOGIC_VECTOR (3 downto 0);
s : out STD_LOGIC_VECTOR (3
METU Northern Cyprus Campus
EEE-248/CNG-232 Logic Design
Spring 2011
Homework #4 due on May 4th (in class)
1. (16 pts.)
i) Convert a T flip-flop (FF) to a JK-FF by including input gates to the T-FF. The gates needed
for the input of the T-FF can be determ
METU Northern Cyprus Campus
EEE-248/CNG-232 Logic Design
Spring 2011
Homework #1 Solutions
1.
(18 pts.)
i. Show how the following decimal numbers are stored as signed binary integers in a digital system.
The system uses 2s complement representation, and h
METU Northern Cyprus Campus
EEE-248/CNG-232 Logic Design
Spring 2010
Homework #4 Solutions
1. (20 pts.)
i) Convert a T flip-flop (FF) to a JK-FF by including input gates to the T-FF. The gates needed
cfw_10 for the input of the T-FF can be determined by m
METU Northern Cyprus Campus
EEE-248/CNG-232 Logic Design
Spring 2011
Homework #1 due on March 16th in class (100 pts)
1.
(18 pts.)
i. Show how the following decimal numbers are stored as signed binary integers in a digital system.
The system uses 2s compl
METU Northern Cyprus Campus
EEE-248/CNG-232 Logic Design
Spring 2011
Homework #3 Solutions
1.
(18 pts.) You are required to construct a combinational circuit, which performs the unsigned
multiplication of a 3-bit binary number X[2:0] with another 2-bit bi
METU Northern Cyprus Campus
EEE-248/CNG-232 Logic Design
Spring 2011
Homework #3 due on April 20th in class (100 pts)
1.
(18 pts.) You are required to construct a combinational circuit, which performs the unsigned
multiplication of a 3-bit binary number X
METU Northern Cyprus Campus
EEE-248/CNG-232 Logic Design
Spring 2010
Homework #2 Solutions
1. (20 pts. ) Given that
A
F
B
i)
ii)
iii)
iv)
v)
implements the F = A B ( XOR function) ;
Implement the 3-input EXOR function G = A B C using only two 2-input XOR
METU Northern Cyprus Campus
EEE-248/CNG-232 Logic Design
Spring 2010
Homework #2 due on March 30th in class
1. (20 pts. ) Given that
A
F
B
i)
ii)
iii)
iv)
v)
implements the F = A B ( XOR function) ;
Implement the 3-input EXOR function G = A B C using only
METU Northern Cyprus Campus
EEE-248/CNG-232 Logic Design - Spring 2011
Homework #5 Solutions
1. (10 pts.) Assuming the asynchronous RESET signal is asserted briefly before the clock begins to oscillate,
what is the count sequence output on A B C for the c