5/18/2016
Boolean Division and Substitution
Using Redundancy Addition and
Removal
1
Substitution
a
w
v=ad+bd+cd+ae
b
p=ke
c
d
k=c+d
e
f t ka kb e
r=p+a
s=r+b
t=ka+kb+e
q=a+b
u=qc+qc+qc
Suppose that a vertex
A function is simplified in complexity
by using

3/28/2016
CAD FOR SEMICUSTOM ASICS
ECE-256D
ASIC = application specific integrated circuit
Semi-Custom = try to design reusing some already
designed parts
CAD = flow through a sequence of design steps and
software tools.
Spectrum of design approaches
LECT

4/23/2016
Boolean networks
1
Node minimization
Problem: Given a Boolean network, optimize it by
minimizing each node as much as possible.
The initial network structure is given.
Node minimization is typically applied after the global
optimization, i.e. di

Technology Mapping
ECE 256d
1
Technology Mapping
Given a set of gates L, called the library, and a Boolean network
G, let M be the set of Boolean networks constructed using gates
from L that are functionally equivalent to G. These are called
mapped networ

Lecture 3
1
Today
Unate recursive paradigm
Unateness
Recursive optimization
Two-level logic minimization
Heuristic logic optimizer Espresso
Complementation
2
1
Monotone functions
A function f is monotone increasing (decreasing) in xj
if f only increases (

ECE-256d
Lecture 2
1
Last time:
Need for logic synthesis,
Basic definitions and operations on logic functions,
Cubes,
Today:
Cofactors
Shannon expansion
2
1
Representation of Boolean Functions
Sum of Products:
A function can be represented by a sum of cub

ATPG in Logic Synthesis
1
ATPG Problem
ATPG: Automatic test pattern generation
Given
Find
A circuit (usually at gate-level)
A fault model (usually stuck-at type)
A set of input vectors to detect all modeled faults.
Core solution: Find a test vector for a

5/23/2016
1
LOGIC LEVEL TIMING
TIMING CLOSURE
Design Entry
Timing more accurate as flow progresses
Synthesis
Sometimes an earlier stage thinks timing is
OK, but it fails a later stage
Place
Timing
Need to repeat one or more steps with
tighter constraints

5/25/2016
1
BOOLEAN MATCHING
EQUIVALENCE OF FUNCTIONS
Equivalence of two functions defined under
of input variables
Permutation of input variables
Negation of output
2
Negation
1
5/25/2016
INTRODUCTION
Combinational
equivalence checking
(CEC)
Known in

Lecture 4
1
Today
Espresso II heuristic
2
1
2-level minimization strategies
Q-M:
1. Generate cover of all primes
G p1 p2 p3n / n
2. Make G irredundant (in optimum way)
Note: Q-M is exact i.e. it gives an exact minimum
Heuristic Methods:
1.
2.
3.
Generate