University of California Santa Barbara Department of Chemical Engineering
ChE10: Introduction to Chemical Engineering Professor Mike Gordon, Fall 2009
Homework #3: due Monday Oct. 19, 2009
(1) Felder & Rousseau #4.6
(2) Felder & Rousseau #4.8
(3) Felder &
VOLTAGE REGULATION BASICS
Power usually enters a system in a form dictated by its generation and distribution characteristics
rather than in a form required by the components within that system. Plugging a computer into a
120 VAC wall outlet provides
RTERM = 39
ZO = 50
ZD = 10
FIGURE 16.4 Series-terminated clock distribution.
are selected to be 39 , the closest standard 5 percent value to ZO ZD. In reality, it is difcult to
than common quartz crystals. Ceramic resonators are used in very low-cost applications wherein accuracy is forsaken for small cost savings. Most digital systems use quartz crystals that cost approximately $1.00, because they are reliable, they provide an
bases are created by exploiting the resonant properties of piezoelectric crystals cut to specic sizes.
Piezoelectricity is the property found in certain crystals whereby slight changes in the crystalline
structure result in a small electric eld, and vice
Clocks are inherently critical pieces of a digital system. Reliable operation requires the distribution
of electrically clean, well timed clocks to all synchronous components in the system. Clocking problems are one of the la
Analog Basics for Digital Systems
quencies generated. These devices are commonly used in digital audio equipment because of their
low overall system cost and high resolution (16 to 24 bits) for frequencies below 100 kHz.
FILTERS IN DATA CONVERSIO
popular. The limitation, of course, is that sigma-delta circuits can be used only at lower sampling
If a sigma-delta circuit cannot be used for one reason or another, it may be practical to operate a
conventional ADC or DAC at a signicantly higher
FIGURE 15.13 Four-bit R-2R ladder DAC.
This expression allows linear control of VO ranging from 0 to within one least-signicant bit position (1/16 in this case
FIGURE 15.12 Sigma-delta ADC circuit.
less than 0, the comparators output is 0, and there is no negative feedback, causing the running difference to increase once again.
tive samples alternated voltage levels about some DC level. A suitable lowpass lter on the DACs
output would remove the high-frequency edges and leave behind a sine wave of half the sampling
frequency as shown in Fig. 15.8.
Lowpass ltering is a critical p
500 s (2 kHz)
FIGURE 15.6 1-kHz sine wave sampled at the Nyquist frequency.
When a data conversion circuit is operated above the Nyquist frequency, aliasing develops, which
distorts the informa
put will cause unacceptable skew to develop with respect to the other pins that are driving only a
single load. Whether this occurs depends on each situations skew tolerance, clock buffer drive
strength, and input impedance of the clock load.
As the numbe
FIGURE 16.3 Single-buffer clock tree.
a single driver and a single load. It is assumed that each load is approximately the same as all other
loads, which is usually the
ripheral IC that is located close to it, the peripherals clock input can be driven directly by the
microprocessors clock output, and all should be okay. Chances are great, however, that the microprocessor must communicate with several peripheral and memor
Voltage Regulation and Power
Power is an obviously critical component of a system, but some engineers have bad reputations for
inadequately planning a systems voltage regulation and power distribution scheme. When power is
bus that operates at hundreds of megahertz. Figure 16.18 shows a hypothetical system architecture
that employs source-synchronous interfaces. There are three ICs, and each IC is connected to the
other two via separate interfaces. Each interface consists o
FIGURE 16.16 Source-synchronous bus.
uniform propagation delay. By the time the signals reach the receiving IC, clock and data are phase
aligned within a certain skew error that is a function onl
A typical high-fan-out clock tree has approximately 0.5 to 1.0 ns of skew resulting from multiple
buffers and PLLs, each contributing several hundred picoseconds of skew and jitter. The question
becomes how much skew a system can tolerate. Skew tolerance
delay-locked loop, or DLL, that produces similar results to a PLL. Instead of controlling a VCO to
vary the phase of the output clock, a DLL contains a many-tap digital delay line through which the
reference clock propagates. According to the detected pha
FIGURE 16.11 Zero-delay buffer on expansion card.
the expansion board between the connector and the zero-dela
uence the suitability of a PLL for arbitrary clock synthesis, including VCO stability and loop-lter
characteristics. VCO stability is improved by ltering its power supply. Typical core clock synthesis
applications in a microprocessor or logic IC may requi
Divide by N
FIGURE 16.12 PLL clock divider.
Clock division by an integer divisor is not very interesting, because it can be done without the
complexity of a PLL. Now lets look at integer multiplication, which does require a PLL. Th
the expansion board, more pins or wires must be used to make the required connections. The increased connectivity increases cost yet does not improve the designs exibility and tolerance of future changes.
A clocks purpose in a system is to provide a regul
of the loop stability problems have been taken care of on a single IC, allowing engineers to use an integrated PLL as a tool and focus on the task of zero-delay clock distribution.
A zero-delay clock distribution circuit contains a PLL whose feedback path
dumb control logic could simply increment the code starting from 0 until the comparators output
changed from high to low. This would mean that an N-bit ADC would require up to 2N cycles to perform a conversion. Instead, a successive-approximation ADC perf
output into smoother transitions that approximate the original signal. The output will never be identical to the original signal, but a combination of sufcient sampling rate and proper lter design can
come very close.
As the ratio of sampling rate to sign
FIGURE 15.10 Flash ADC circuit.
requires 4,095 parallel comparators. When a voltage is applied to the ash circuit, one or more comparators may emit a logic 1. A priori