University of California Santa Barbara Department of Chemical Engineering
ChE10: Introduction to Chemical Engineering Professor Mike Gordon, Fall 2009
Homework #3: due Monday Oct. 19, 2009
(1) Felder & Rousseau #4.6
(2) Felder & Rousseau #4.8
(3) Felder &
+ 0.5*2 ; x = 110.55 - 3) = 0.240L. FLEXURAL CAPACITY OFA
COMPOUND BEAM A Wl6 x 45 steel beam in an existing structure
was reinforced by welding an WT6 x 20 to the bottom flange, as in Fig.
28. If the allowable bending stress is 20,000 lb/in2 (137,900 kPa
vI
R
vI
+
C
+
vO
C
vO
R
FIGURE 14.25 First-order active lters.
pass and highpass active lters implemented with op-amps. These simple lters buffer a passive lter with a noninverting op-amp stage. In this example, the congurations are for unity gain, althou
vI
+
vO
VREF
FIGURE 14.28 Open-loop voltage comparator.
when reading through a comparators data sheet. Specications such as VIO, IBIAS, IIO, and gain are
observed. However, op-amps and comparators are optimized for different characteristics. Op-amps
are d
It can be difcult to achieve a perfectly monotonic signal because of ambient noise in a system. If
the signal can be guaranteed to rise and fall quickly, the window of opportunity for noise to trigger
an undesired response at VREF is limited. This is how
In many cases, it is convenient to set R1 = R2 and C1 = C2, in which case fC is given by
1
f C = -2RC
Aside from providing amplication, a benet of using op-amps to build lter stages is that multiple stages can be cascaded to implement more advanced lters.
VO(MAX)
VO
0
High-to-Low
Threshold
0
Low-to-High
Threshold
VI
FIGURE 14.31 Hysteresis loop.
The degree of hysteresis designed into a comparator circuit is determined by the difference between the high and low thresholds. A small difference is less toleran
R2
R1
vIN
virtual loop
vIN+
vO
+
R1
R2
FIGURE 14.24 Single op-amp difference amplier.
By superposition, the linear partial terms, vO+ and vO , are summed to yield a nal output expression
that clearly shows that this circuit is a difference amplier.
R2
R2
ready low. Similarly, vI must be reduced to a lower voltage threshold to counteract the pull-up effect
when the output is already high.
Another benet of hysteresis is that it snaps the comparator input voltage above or below VREF
once the output state tra
When an analog signal is applied to an ADC, the ADC evaluates the instantaneous sample of that
signal against predened high and low voltage extremes that dene an allowable input range for that
ADC. As shown in Fig. 15.1, the ADC overlays a range of number
With the resistors determined, the next step is to calculate the required reference voltage to
achieve the desired thresholds. Using the slightly simpler expression for VTLH provides the following
result:
R1 + R2
V TLH = 1.8 = V REF - = V REF ( 1.12 ) , V
CHAPTER 15
Analog Interfaces for Digital
Systems
The intersection of analog and digital worlds has given rise to a tremendously broad range of applications for digital systems. Digital cellular telephones, enhanced radar systems, and computerized
engine c
100 s
sampling
interval
Voltage
0 s
500 s
1000 s
1500 s
2000 s
Time
FIGURE 15.3 1-kHz sine wave sampled at 10 kHz.
spaced sampling intervals are shown at an arbitrary phase offset from the sine wave to illustrate the
arbitrary alignment of samples to the
In circuit analysis terms, a single input voltage can be isolated from the others by tying each other
input to ground and then evaluating the circuit as if that single input voltage were the only input
present. This analysis method can be applied to each
the rivet diameter. However, to allow for damage to the adjacent metal
caused by punching, the effective diameter of the hole is considered to
be 1A in (3.18 mm) larger than the rivet diameter. Refer to Fig. 55&, c,
and d. Equate the tensile stress at eac
one of tension or compression, proceed in this way: Select a particular
joint and proceed around the joint in a clockwise direction, listing the
letters in the order in which they appear. Then refer to the force polygon
pertaining to (b) Force polygon FIG
derive the following equations for the midspan deflection under the unit
load: When a < Lf2, y = (3L2 a - 4a3 )/(48EI). When a < L/2, y = [3L2
(L - a) - 4(L - a)3 ]/(48EI). 2. Position the system for purposes of
analysis Position the system in such a mann
algebraic signs disclose that AJ is compressive and HJ is tensile. Record
these results in Table 2, showing the tensile forces as positive and
compressive forces as negative. 4. Determine the forces at another joint
Draw a free-body diagram of the pin at
find the tension Tin the tie rod: ^Mc= 360(12.8) -7.8f= O T= 591 Ib
(2628.8 N) FIGURE 3 Tie rod 5. Verify the computed result Draw a
free-body diagram of member BC, and take moments with respect to C.
The result verifies that computed above. GRAPHICAL ANA
BENDING OFA CIRCULAR FLATPLATE A circular steel plate 2 ft
(0.61 m) in diameter and 1A in (12.7 mm) thick, simply supported along
its periphery, carries a uniform load of 20 lb/in2 (137.9 kPa) distributed
over the entire area. Determine the maximum bendin
4. Determine the minimum force in the member To secure the minimum
value of Vcd, apply uniform load continuously in the interval of.
Perform the final calculation by proportion. Thus, Cdmin/Cdmax = area
azy/area jhg = -(2/3)2 = 9. Then O/min = - O; /. Vde
members to find / for the built-up beam. Thus, for the W16 x 45: k =
3.99 in (101.346 mm); 10 + AIf 583 + 13.24(3.99)2 = 793 in4 (33,007.1
cm4 ). For the WT6 x 20: & = 8.06 - 3.99 + 4.89 = 8.96 in (227.584
mm); I0 + Ak2 = 14 + 5.89(8.96)2 = 487 in4 (20,27
establish a feasible rivet pitch. From an earlier calculation procedure in
this section, Rss = 6630 Ib (29,490.0 N). Then T= 7425(2) = 663Ow; n =
2.24. Use the next largest whole number of rows, or three rows of rivets.
Also, Lmax = 3(6630)/7425 = 2.68 in
(7.94 mm). Hence, the weld capacity = 5(600) 3000 Ib/lin in (525,380.4
N/m); L = weld length, in (mm) = P/capacity, Ib/lin in = 62,920/3000 =
20.97 in (532.638 mm). 3. Compute the joint dimensions In Fig. 60, set c
= 5 in (127.0 mm), and compute a and b b
reaction at B is directed along BC. Because the unit load and the two
reactions constitute a balanced system of forces, they are collinear.
Therefore, J lies on the action line of the unit load. Alternatively, the
location of the neutral point may be esta
is satisfactory. 4. Design the splice plates To the left of the centerline,
each splice plate bears against the left half of the rivet. Therefore, the
entire load has been transmitted to the splice plates at cc, which is the
critical section. Thus the ten
VOUT = Data
Data[N1:0]
Sample Clock
VOMAX
2N1
Sample
Input
Register
FIGURE 15.2 Conceptual digital-to-analog converter.
is converted back to analog with the rounding made permanent. The exact magnitude of the original
analog signal is lost. The process of
VREF
R
+
R
+
R
+
R
Priority
Encoder
Digital Samples
+
R
+
R
+
R
Output from
Sample/Hold
FIGURE 15.10 Flash ADC circuit.
requires 4,095 parallel comparators. When a voltage is applied to the ash circuit, one or more comparators may emit a logic 1. A priori
ripheral IC that is located close to it, the peripherals clock input can be driven directly by the
microprocessors clock output, and all should be okay. Chances are great, however, that the microprocessor must communicate with several peripheral and memor
of the loop stability problems have been taken care of on a single IC, allowing engineers to use an integrated PLL as a tool and focus on the task of zero-delay clock distribution.
A zero-delay clock distribution circuit contains a PLL whose feedback path