EE 671 (VLSI Design) : Assignment
Name:- Muhammed Tahir Patel
Roll no.:- 111030002
Solutions
Given :- Eg = 1.1eV, Ef (Si) = 4.6eV, Work function (gate) = 4.4eV,
14
p=N A =10 /cm
3
, kT/|q| =25mV
1) To find: - EFp.
We know,
p=n i e
14
10
10 =10 e
E iE Fp
k
Towards a MOS model
Madhav Desai
August 3, 2014
Sources
The books by Streetman and Leblebici/Kang, also Tsividis, The
MOS Transistor, McGraw-Hill.
Energy and potential
Some basic assumptions:
A particle at rest (e.g. an electron), when at innity, has
ener
Logical Effort: Designing for Speed
on the Back of an Envelope
Ivan E. Sutherland
Robert F. Sproull
Sun Microsystems, Inc.
Mountain View, CA 94043
Designers know to use strings of inverters with geometrically increasing sizes
to drive large capacitive loa
IEEE JOURNAL OF SOLID-STATECIRCUITS, VOL. 25, NO. 2, APtUL 1990
584
Alpha-Power Law MOSFET Model and its
Applications to CMOS Inverter Delay and
Other Formulas
TAKAYASU
SAKURAI,
MEMBER,IEEE, AND A. RICHARD
Abstract A simple yet realistic MOS model, namely
EE671: MAGIC tutorial addendum
Nanditha Rao
September 25, 2013
This document contains installation information for the magic layout tool,
mentions a few important points about its usage, provides pointers to already
existing tutorials and provides help on
( HOMEWORK # 1 ) Write out details of some proofs and analysis ( done
during today's lecture # 4 ) : Thursday 30th July 2015
Ex. 1 : Find a shortest Hamiltonian Walk in the FSM graph ( described on
blackboard in today's lecture ).
Ex. 2 : Consider a tourn
Consider a Finite State Machine. It can be modeled as a directed graph, nodes
representing the states of the FSM, and the directed edges ( arcs ) representing the transitions of
the FSM.
Assume that the FSM as an initial state, which it always enters on R
(HOMEWORK # 3 ) Based on lecture#7 Monday 10th Aug 2015
1. Write pseudo-code for recursive algorithm (outlined briefly in lecture#7) for problem of Towers of
Hanoi
1. Prove that the recursive algorithm for Towers of Hanoi needs (2-raised-to-n MINUS 1) ste
REQUIERED READING) Analysis of running time of algorithm
Towards the end of today's lecture, I introduced definition of big-Oh, THETA, small-Oh etc. a little
DEFENSIVELY.
We will make our life easier by CREATING ESTIMATES, T_A ( n ) in some suitable algeb
Homework # 2
Q.1 : Consider the 7-bridges of Koenigsberg problem. Suppose the cost (toll
tax) of traversing any of the 4 bridges between the bigger island ( node B
) and the banks of the river ( nodes A and C ) are VERY CHEAP, say 100. On
the other hand t
Hints and Outlines for solutions of questions in Midsem-ee677_2015 examination
(outline of ) Solution to Q.1
Use the same, natural graph model of the PDN, and nd all paths
from the output node to the ground node.
To each path, associate a
boolean-product
501
Sec. 14.2 Recurrence Relations
14.2
Recurrence Relations
Recurrence relations are often used to model the cost of recursive functions. For
example, the standard Mergesort (Section 7.4) takes a list of size n, splits it in half,
performs Mergesort on e
Graph Theory
1
Graphs and Subgraphs
Definition 1.1. A multigraph or just graph is an ordered pair G = (V, E)
consisting of a nonempty vertex set V of vertices and an edge set E of
edges such that each edge e E is assigned to an unordered pair cfw_u, v wit
EE 671: MAGIC tutorial
A. Mittal, M. Bose, N. Karanjkar
October 7, 2011
Implement a 31-stage ring oscillator, each of whose stages is a 20/10
inverter (in the TSMC 180nm technology).
1. First design the layout of a single stage. The transistors should be
MOSIS LAMBDA DESIGN RULES
3 sets of design rules:
1) SCMOS: valid for technologies with 2>1 m
2) SCMOS_SUBM: valid for technologies with 0.25<21 m
3) SCMOS_DEEP: valid for technologies with 20.25 m
LAYOUT DESIGN RULES: an overview
Layer
GDS
CIF
CIF
Synony
EE 671: NGSPICE tutorial
Madhav P. Desai
August 15, 2014
1
NGSPICE
NGSPICE (or SPICE3) is a circuit simulator which allows you to describe a
circuit as an interconnected network of circuit elements (resistors, capacitors,
controlled sources, voltage and c
Mid-semester test: EE671 VLSI Design
Madhav P. Desai
8:30-10:30am, September 9, 2014
Unless otherwise mentioned, the reference technology in all problems is
the TSMC 180nm N-well process introduced in class. All transistors are
minimum length (2 = 0.18) u
Practice Problem Solutions: EE671
November 3, 2014
Some useful data:
CAPACITANCE PARAMETERS N+
P+ POLY
Area (substrate)
973 1161 104
Area (N+active)
8355
Area (P+active)
8187
Fringe (substrate)
265 221
Overlap (N+active)
708
Overlap (P+active)
632
UNITS
a
Power Distribution in VLSI Systems
Madhav P. Desai
September 25, 2014
1
The Problem
Consider the system schematic in Figure 1. An ideal voltage source is providing
power to two subsystems (modules) G1, G2. The module G1 is charging a load
capacitance C, a
EE 671 (VLSI Design) : Assignment
Name:- Muhammed Tahir Patel
Roll no.:- 111030002
Solutions
Given :- Eg = 1.1eV, Ef (Si) = 4.6eV, Work function (gate) = 4.4eV,
, kT/|q| =25mV
1) To find: - EFp.
We know,
2) Vfb = ?
3) At inversion,
4) Threshold voltage is
Setup and Hold times of a Master-Slave Flip-Flop
Madhav Desai
September 30, 2014
A delay element: the master-slave positive-edge-trigerred
D-ipop
D
U
Q
Clock
Figure: Master-slave positive edge triggered D-ipop.
Setup, hold and delay times of the positve-e
Assignment 4: EE 671
Madhav P. Desai
September 22, 2014
Design a four-input parity circuit whose input capacitance is Cin = 10, and
output load capacitance is Cout = 1000 (Cin and Cout are specied in minimum
inverter units, where a minimum inverter unit i
Solutions to Assignment 1: EE 671
Madhav P. Desai
August 18, 2014
We use E0 = 0eV to represent the energy level of free space. Assume that
the dielectric constant of SiO2 is 3.9 and that of Si is 11.68. The band-gap
Ec Ev of Silicon is 1.1eV , and the Fer
EE 671: RC delays and the use of buers
Madhav P. Desai
September 23, 2014
1
The Problem
Consider the following situation (Figure 1). A driver D is attempting to respond
to a transition at its input node A by causing the input node B of a receiver
to switc
A summary of the method of logical eort
Madhav P. Desai
September 2, 2014
The method of logical eort (as formalized and presented in the book by
Sutherland, Sproull and Harris) is basically a path based optimization technique.
The heart of the method is t
A Hybrid Algorithm for LTL Games
Saqib Sohail1 , Fabio Somenzi1 , and Kavita Ravi2
1
University of Colorado at Boulder
cfw_Saqib.Sohail,[email protected]
2
Cadence Design Systems
[email protected]
Abstract. In the game theoretic approach to the synthesis