EE633 Fall2011 HW#6 (Due December 12, 2011)
In all questions break ties in alphabetical order.
1. Perform a single pass of Kernighan and Lin algorithm on the circuit in Figure1 using
cfw_bcde, afgh as the initial solution.
Figure1
2. Perform a single pass
EE633 Homework 5 due on Nov 21, 2011
Estimate the power of the given circuits for input signal probabilities assigned to you in
tables. Supply power is 2.4 V and operation frequency is 100 MHz. To simulate the
power dissipation for transitions between dif
EE633 Fall 2011
Homework 3 due on Oct 26, 2011
Show all your work when solving the following questions.
1. For circuit1 depicted below:
a) Find the collapsed fault set.
b) Using deductive fault simulation with test vector 11010, which faults can be detect
EE633 Fall 2011
Homework 1 due on Oct 5, 2011
1. Derive a binary decision diagram for the function
Z(x1,x2,x3,x4) = (1,3,6,7,8,11,12,13,15)
2. Determine whether the following cubes can be cubes of a function Z(x1,x2,x3,x4). If so,
explain why. If not, how
MAC Unit (267K)
Placement took 44 sec, routing took 289 sec
Area = 320x320um, used 7 metal layers
MAC Unit (267K)
M1
M2
M3
M4
M5
M6
MAC Unit (267K)
M7
MAC Unit (267K)
Placement
Routing
MAC Unit (267K)
Placement
The process of arranging the circuit components on a layout surface.
Inputs: A set of xed modules, a netlist.
Goal: Find the best position for each module on the chip according to
appropriate cost functions.
Considerations: routability/chann
Routing
placement
Generates a "loose" route for each net.
Assigns a list of routing regions to each net without
specifying the actual layout of wires.
global routing
Global routing
detailed routing
Finds the actual geometric layout of each net within
the
ALGORITHMS FOR VLSI DESIGN AUTOMATION
1
GENERAL-PURPOSE OPTIMIZATION METHODS
THE UNIT-SIZE PLACEMENT PROBLEM
PROBLEM DEFINITION:
* input: a netlist.
* all cells have dimensions
1 1.
* a grid position should be assigned to each cell.
* goal: minimize total
ALGORITHMS FOR VLSI DESIGN AUTOMATION
1
TRACTABLE AND INTRACTABLE PROBLEMS
OPTIMIZATION PROBLEMS
Problem: a general class, e.g. the shortest-path problem for directed
acyclic graphs.
Instance: a specific case of a problem, e.g. the shortest-path problem
i
1
ALGORITHMS FOR VLSI DESIGN AUTOMATION
GRAPH THEORY AND COMPUTATIONAL COMPLEXITY
GRAPH THEORY
Graph: A mathematical object representing a set of points and interconnections between them.
Notation: G(V, E), where:
*V
is
the
vertex
set:
cfw_v 1, v 2, v 3,
ALGORITHMS FOR VLSI DESIGN AUTOMATION
1
DESIGN METHODOLOGIES AND SURVEY OF TOOLS
THE VLSI DESIGN PROBLEM
Realize a given specification on silicon, optimizing the following entities:
* area (yield)
* power dissipation
* speed
* design time
* testability
Op
A Linear-Time
Heuristic
for Improving Network Partitions and R.M. Mattheyses
C.M. Fiduccia
General Electric Research and Development Center Schenectady, NY 12301
An iterative mincut heuristic for partitioning networks is presented whose worst case computa
Floorplanning, Placement, and Pin Assignment
Partitioning leads to
Blocks with well-dened areas and shapes (xed blocks).
Blocks with approximated areas and no particular shapes (exible
blocks).
A netlist specifying connections between the blocks.
Obj