RAM, ROM, Registers,
INPUT - OUTPUT
Building Blocks for Digital Architectures
A Generic Digital Processor
Interconnect:
Switches,
Arbiters, Bus,
MEMORY
CPU
CONTROL
DATAPATH
Arithmetic Unit:
Adder, Multiplier,
Shifter, Comparator,
Intro to Logic Design
ECE 620 Dr. R. ROOSTA H.W # 3 SOLUTIONS
P1) This can be done by trial and error. By specifying both the entries as '0', let's see if we come up with a distinguishing sequence: Test for distinguishing sequence:
Initial state Output sequence Final state
010
ECE 620 Dr. R. ROOSTA H.W # 2
1) An incompletely specified machine has a state table as shown below. Use Meisel method to find a minimal closed cover for this machine.
2)
The machine M is to be realized as shown below. Derive a state table description for
Chapter 4
Decomposition of
Synchronous Circuits
Dr. Ramin Roosta
California State University, Northridge
Fall 2014
1
Introduction
It is often convenient to realize a sequential circuit as an interconnection of two
or more subcircuits.
Designer must first
Channel Based
Asynchronous Circuit
Design
part I
Dr. Ramin Roosta
California State University, Northridge
Fall 2014
1
Asynchronous Channels
Channel: A bundle of wires and a protocols for communicating
data/control called a token
Data/control encoding: Dua
Channel Based
Asynchronous Circuit
Design
part II
Dr. Ramin Roosta
California State University, Northridge
Fall 2014
1
Asynchronous Channels
Channel: A bundle of wires and a protocol for
communicating data/control called a token
Data/control encoding: Du
Metastability in
Asynchronous Circuits
Dr. Ramin Roosta
California State University, Northridge
Fall 2014
1
Metastability
Metastability
Mean time between failures (MTBF)
Signal is stuck at an in-between state
What Causes Metastability?
Synchronous(system
Chapter 7
Synchronous vs.
Asynchronous Design
Dr. Ramin Roosta
California State University, Northridge
Fall 2014
1
No clock skew
Asynchronous circuits by definition have no
globally distributed clock, there is no need to worry
about clock skew
Synchronous
Chapter 4
Decomposition of
Synchronous Circuits
Dr. Ramin Roosta
California State University, Northridge
Fall 2014
1
Introduction
It is often convenient to realize a sequential circuit as an interconnection of two
or more subcircuits.
Designer must first
ECE 620
Dr. R. ROOSTA
H.W # 7 SOLUTIONS
P1) f = wxy + (w + z)(w' + y') = wxy + ww' + wy' + w'z + y'z
The term ww' indicates that there is static 0 hazard.
To find out about the static 1 hazard, let's make the karnaugh map:
y,z
w,x
00
01
11
10
00
1
1
01
1
Synchronous _ Asynchronous
Design Flows
Dr. Ramin Roosta
California State University Northridge
Need for Proper Design Techniques
Increasing semiconductor needs
More transistors on single chip
Small transistors consume less power
Leakage currents, cross t
Low Power Design
Techniques
EE620
R. Roosta
Power Dissipation in a CMOS device
Dynamic Power Dissipation:
2
Pswitching p(C load VDD
f clk )
2
Pshort circuit I SCVDD
Static Power Dissipation:
Pleakage I
2
leakage DD
V
Total Power Dissipated:
Ptotal Pswitch
Chapter 11
Design of Digital Circuits
Using Algorithmic State
Machine (ASM)
Dr. Ramin Roosta
California State University, Northridge
Spring 2013
1
Introduction
In designing digital circuits, a good design style is to design from the top down, maintaining
CHAPTER 9: Asynchronous Circuit State Assignment
9.0 Introduction
In designing a circuit from a problem statement, there comes a point when it is
necessary to assign state variables to represent the various states of the machine. In a
previous section, we
Chapter 8
Asynchronous Design
Dr. Ramin Roosta
California State University, Northridge
Fall 2014
1
Asynchronous Circuits
2
Requirements for the synchronous circuit to function
with stability:
Two requirements must be met:
1.T1 > tff -itisessentialthattheF
Chapter 5:
Sequential Machines;
Partitioning and
Dr. Ramin RoostaFunctional Testing
California State University, Northridge
Fall 2014
1
Introduction
The way we assign states in the state table affects the complexity and
testability of the machine.
In this
SEU Immunity Is Your
Design Really Safe?
Dr. Ramin Roosta
California State University Northridge
EE 620
Contents
What are SEUs?
Sources of SEUs in Terrestrial Applications
Neutrons and Alpha Particles
Consequences of SEUs
Test Results
Neutrons
Alpha parti
Chapter 2
State Table
Minimization
Dr. Ramin Roosta
California State University, Northridge
Fall 2014
Introduction
The state table is one of the most basic ways to
represent a synchronous machines operation.
state table can be optimized to include fewer s
Chapter 1
Basics of Logic Algebra
Dr. Ramin Roosta
California State University, Northridge
Fall 2014
Introduction
In this chapter:
Fundamental
concepts of logic design
Discussion of Boolean algebra
Logic gates
Combinational circuit minimization
Flip-
Chapter 10:
Hazard Detection and
Elimination
In Digital Systems
Dr. Ramin Roosta
California State University, Northridge
Spring 2014
1
Hazards (Glitches) Type
Static Hazard: the possibility of a single momentary transient in an output
signal that should h
Chapter 9:
Asynchronous Circuits
State Assignment
Dr. Ramin Roosta
California State University, Northridge
Spring 2014
1
Introduction (Asynch. Design)
State Assignment: The way in which state variables are assigned
greatly effect the efficiency of the mac
Channel-based Asynchronous
Design
California State University, Northridge
Prof. Dr. Ramin Roosta
By
Natekar Suyog (SID#102059566)
Deshpande Nikhil (SID#101905763)
Asynchronous Channels
y Channel: A bundle of wires and a protocols for communicating data/co
ECE 620
Dr. R. ROOSTA
H.W # 8 SOLUTIONS
1) The composite Karnaugh map for the next state and external outputs for the given
state diagram is shown as follows :
2) The logic hazard free equations for the circuit are :
Y
=A.B
SUM
= A' . B + A . B' = A + B
C
ECE 620 Dr. R. ROOSTA H.W # 7
1) Does the machine with the following state equation contain any static-0 hazard? Does it contain static-1 hazard? f = wxy + (w + z) (w' + y')
2) Briefly explain what an essential hazard is, what causes it and how it can be
EE 620 N Dr. R. ROOSTA H.W # 6
1) a) For the following flow table, find the shared row assignment showing all transitions. b) Find the Y matrix specification for the shared row state assignment for the machine in Q.1(a).
2)
For the flow table given below,