PLACEMENT
The Problem
Given objects to be placed on carrier.
Given constraints on where objects can be placed.
Given net list.
Place elements such that:
* Total area is minimal
or * Carrier is routable
or * Power dissipation is uniform
.
.
.
or * Some com

Clock Routing
ECE 624
Digital Systems Design Automation
Clock Network Requirements
Clock network distributes clock signal throughout the chip
Requirements:
Zero skew: all clock signals must arrive at the same time
Sharp edges: slew rates (rise/fall times)

Genetic Algorithms
1
2
Genetic Algorithms (GA)
A class of probabilistic search algorithms
Inspired by natural genetics and biological evolution
Uses concept of survival of fittest
Originally developed by John Holland (1975)
3
Genetic Algorithms (GA)
Simul

Fiduccia-Mattheyses (F-M)
A Heuristic Partitioning Algorithm
Dr. Ramin Roosta
California State University, Northridge
PARTITIONING
Partitioning : assignment of logic components to physical
packages
-Circuit is too large to be placed on a single chip
-I/O

Implementation & Comparison of
VLSI Cell Placement Algorithms
EE624
1
Content
Introduction
Common data structure
Implementation of Simulated-annealing
algorithm
Implementation of Genetic algorithm
Implementation of Force-directed algorithm
Results compari

Heuristic Techniques in
Design Automation
EE624
1
2
Definition of a Heuristic
Dictionary: Serving to discover
A. I.:
A technique to search a solution space
for a good feasible solution
S. Lin:
Any technique, procedure, method, or
algorithm that produce

ECE 624
Homework # 4 (Algorithms)
1.
(Minimum Spanning Tree)
a. Prove that PRIMs procedure, presented in class, produces a MST.
b. Determine the complexity of this algorithm given A = [aij], where aij is the distance
between nodes i and j.
c. Carry out th

Routing Algorithms for
Standard cell with Emphasis on
OTC
ECE 624
Digital Systems Design Automation
Agenda
Introduction
Basics
Various Algorithms for routing
OTC (Over the Channel Routing)
Conclusions
Basic Algorithms
Breadth First(Two Terminal Shortest
D

Placement
ECE 624
Digital Systems Design Automation
Problem Formulation
Given a set of cells (modules) of fixed
dimensions and the interconnections between
them
Find:
Position of each cell such that
(i) no overlaps (with enough routing space)
(ii) minimiz

Genetic Algorithms
R. Roosta
1
2
Genetic Algorithms (GA)
A class of probabilistic search algorithms
Inspired by natural genetics and biological evolution
Uses concept of survival of fittest
GA originally developed by John Holland (1975)
3
GA -general conc

ALGORITHIMS HEURISTICS
AND COMPLEXITY
ECE 624
Digital Systems Design Automation
Combinatorial Theory deals with problems involved in
enumeration, counting, searching process, finding closed form
solutions to properties of the above and in addition, where

Circuit Partitioning
EE624
1
Partitioning a circuit C
2
C partitioned into three sub-circuits
3
More partitioning examples
(a) A circuit to be partitioned
(b) Partition using cutline C1
( four chip to chip interconnects
(c) Partition using cutline C2
(on

9 - Noise Sources
EE624
R. Roosta
California State University , Northridge
Outline
Background
Noise in Digital Systems
Capacitive Crosstalk
Inductance Effects
Ground Bounce
IR Drop
Skin Effect
Electromigration
EMI
On and Off Chip Clock Frequencies
Sources

Algorithms, Heuristics,
and Complexity
ECE 624
Digital Systems Design
Automation
Combinatorial Theory
Deals with problems involved in enumeration, counting, searching process,
finding closed form solutions to properties of the above and in addition, where

Computer Aided Design of
Digital Systems
EE624
Ramin Roosta
California state University Northridge
Course Objectives
EE624 : CAD course aimed at graduate students who want broad exposure
to the algorithms and data structures of modern VLSI
design tools
EE

Part 2 of Heuristics: Simulated annealing
1
Introduction: Bi-partitioning a graph
A simple initial assignment
Cut=6
Nodes can have weights e.g. associated with area or power
Edges can have weights e.g. associated with criticality or bus
width
2
A single

Circuit Partitioning
EE624
R. Roosta
1
Partitioning a circuit C
2
C partitioned into three sub-circuits
3
More partitioning examples
(a) A circuit to be partitioned
(b) Partition using cutline C1
( four chip to chip interconnects
(c) Partition using cutl

Floorplanning
ECE 624
Digital Systems Design Automation
Outline
Introduction and definitions
Mixed Integer Linear Program Solution
Successive Augmentation
Simulated Annealing-based Approaches
Shape Function Computation
Considering Various Constraints
Hier

Heuristic Techniques in
Design Automation
EE624
1
2
Definition of a Heuristic
Dictionary: Serving to discover
A. I.:
A technique to search a solution space
for a good feasible solution
S. Lin:
Any technique, procedure, method, or
algorithm that produce

Routing & Congestion Analysis
ECE624
Metal Layer Stack
Layer Thickness Distribution.
Wider wires on higher metal layers enable signals to travel
faster and further than for wires on thinner metals
As the processes get smaller and smaller, metal layers
w

EE 624
Channel Routing Problem
Route between a top row and bottom row (pins with the
same number have to be connected)
Using only two metal layers
Overall area of the channel i.e. minimized Height of the
channel
Routing
Global Routing
Detailed Routing

ECE 624
Homework #1 (Graph Theory)
Questions based on introduction to course:
1. Why is it faster to produce a gate array than a standard cell ASIC?
2. Why does a circuit implemented on an FPGA run slower than the same circuit
implemented as a gate array?

Term Paper On Clean Rooms, Lithography and CMP
CLEAN ROOMS, LITHOGRAPHY AND
CMP
California State University, Northridge
Page 1
Term Paper On Clean Rooms, Lithography and CMP
Introduction:
Semiconductor fabrication is used to create chips, the IC that are

Graph Theory
and
Applications
Graph Theory and Applications
Paul Van Dooren
Universit catholique de Louvain
Louvain-la-Neuve, Belgium
Dublin, August 2009
Inspired from the course notes of V. Blondel and L. Wolsey (UCL)
Appetizer
Graph theory started with

R. Roosta
EE624
1. Technology Node
A technology node or generation refers to the size of the featureselements that make up the structures on a chip- fabricated on a
silicon chip.
2. Band Gap
The band gap (or energy gap) in a material is the energy
differe

ECE 624
Homework #1 (Graph Theory)
Questions based on introduction to course:
1. Why is it faster to produce a gate array than a standard cell ASIC?
2. Why does a circuit implemented on an FPGA run slower than the same circuit
implemented as a gate array?

Heuristic techniques in
design automation
1
2
Definition of a heuristic
Dictionary: Serving to discover
A. I.:
A technique to search a solution space
for a good feasible solution
S. Lin:
Any technique, procedure, method or
algorithm that produces a fea

Placement
Steinberg Algorithm
Force Director method
EE624
1
Partitioning a circuit C
1.
Steinberg's technique
Goal: Take a given placement and attempt to improve it (Assume slotted Problem)
General approach: (Assume slotted problem)
1) Select subset of el

ELECTROMIGRATION
ECE 624
ELECTROMIGRATION
What is it?
History
Causes
Factors Affecting EM
Effects
Practical Implications
Avoidance Technique
What is it?
Momentum transfer from flowing
electrons into the ions that make up a
wire connect
Similar to th

Heuristic Techniques in
Design Automation
EE624
1
2
Definition of a Heuristic
Dictionary: Serving to discover
A. I.:
A technique to search a solution space
for a good feasible solution
S. Lin:
Any technique, procedure, method, or
algorithm that produce