Computer Aided Design of
Digital Systems
EE624
Ramin Roosta
California state University Northridge
Course Objectives
EE624 : CAD course aimed at graduate students who want broad exposure
to the algorithms and data structures of modern VLSI
design tools
EE

ECE 624
Homework #1 (Graph Theory)
Questions based on introduction to course:
1. Why is it faster to produce a gate array than a standard cell ASIC?
2. Why does a circuit implemented on an FPGA run slower than the same circuit
implemented as a gate array?

Term Paper On Clean Rooms, Lithography and CMP
CLEAN ROOMS, LITHOGRAPHY AND
CMP
California State University, Northridge
Page 1
Term Paper On Clean Rooms, Lithography and CMP
Introduction:
Semiconductor fabrication is used to create chips, the IC that are

Graph Theory
and
Applications
Graph Theory and Applications
Paul Van Dooren
Universit catholique de Louvain
Louvain-la-Neuve, Belgium
Dublin, August 2009
Inspired from the course notes of V. Blondel and L. Wolsey (UCL)
Appetizer
Graph theory started with

R. Roosta
EE624
1. Technology Node
A technology node or generation refers to the size of the featureselements that make up the structures on a chip- fabricated on a
silicon chip.
2. Band Gap
The band gap (or energy gap) in a material is the energy
differe

ECE 624
Homework #1 (Graph Theory)
Questions based on introduction to course:
1. Why is it faster to produce a gate array than a standard cell ASIC?
2. Why does a circuit implemented on an FPGA run slower than the same circuit
implemented as a gate array?

Computer Aided Design of
Digital Systems
EE624
Professor Ramin Roosta
Dept.of ECE
California state University Northridge
Course Objectives
EE624 is a CAD course aimed at graduate
students who want broad exposure to the
algorithms and data structures of mo

ECE 624
Homework #1 (Graph Theory)
Why is it faster to produce a gate array than a standard cell ASIC?
because fabrication steps are needed for standard cell design, however for gate array
design uses prefabricated chip with active devices like NAND-gates

YASAMAN DIANATPEY
ECE 624 Homework #2 (Graph Theory)
1. An indirected graph is self-complementary if it is isomorphic to its complement. Show
that there are exactly two self-complementary graphs having five vertices.
2. Give a precise description of a cho

ECE 624
Homework #1 (Graph Theory)
1.
Why is it faster to produce a gate array than a standard cell ASIC?
Sol.
Because for a standard cell design all the fabrication steps are necessary, while for
a gate array design only a couple of processing steps are