Course Description ECE 526
ECE 526: Verilog HDL for Digital Integrated Circuit Design Prerequisite: ECE 320/L. Corequisite: ECE 526L. This course covers use of Verilog Hardware Description Language for the design and development of digital integ
More Misuse of defparam
Another defparam Problem
Syntactically, there is no limit to the
number of times a parameter can be
redefined via defparam.
If a parameter is redefined in multiple files,
there is no guaranteed order of execution.
General Course Policies
Attendance is never taken
Lab attendance is NOT optional.
Everyone must attend every lab session and
be there on time.
You must demonstrate that you yourself are
doing the lab, not copying from someone
Yet another form of Boolean operators, this
one, like Logical Operators, only producing
a single bit output.
Same symbols, different application.
Reduction operators only operate on a
ECE 526L: Digital Design with Verilog and SystemVerilog Laboratory
Lab 0: Tool access and directory setup
ECE 526 lab uses Red Hat Linux operating on HP computers. Familiar Windows commands and
programs will not work. Gaining familiarity with Linux/UNIX i
Experiment # 1
Familiarization with Linux and the Synopsys VCS Simulator
Note that there frequently is more than one way to accomplish a task in Linux. As you
develop proficiency with this operating system, you may find procedures that will work
as well a
Experiment #2, Structural Modeling of a JK Flip-Flop
In this experiment, you will model and test a JK flip-flop. You will incorporate gate delays
and study their effects and you will study the operation of the four Verilog system tasks for
Experiment #3, Hierarchical Modeling
In this experiment, you will model an edge triggered flip-flop using a hierarchical
modeling approach. You will then model and test an 8-bit register using an array of
instances of this flip-flop.
Using primitive ga
Experiment #4, Behavioral Modeling of a 5-bit Counter
1. Create a behavioral model of a 5-bit reloadable up counter.
a. Use the following port data
Single bit inputs: Clock, Reset, Enable,
Load Five bit Data input
Five bit Count output.
Save your file as
Experiment #6, Carry Select Adder
The attached circuit diagram represents a 6-bit Carry Select Adder. It is one of the
fastest adder circuits and has much better performance than a regular Ripple Carry
Adder. Each adder stage, with the exception of the fi
Experiment #7, Register File Models
A register file operates similarly to random access memory but is made from flopflops
rather than DRAM or SRAM cells. A register file would consume far more power and
take far more area than a true memory of the same ca
Experiment #5, Scalable Multiplexer
1. Create a Verilog model of a scalable multiplexer, scale_mux.v. Use the following
module scale_mux(A, B, SEL, OUT)
a. The size of the ports is determined by a parameter,
Experiment #8, Arithmetic-Logic Unit Modeling
In this experiment, you will model an arithmetic-logic unit, or ALU.
1. Create a Verilog module of the ALU. Use a header similar to the one below or write
one using SystemVerilog constructs:
Discussed why designs are done in HDL
Overview of simulation algorithms
You have no control over which algorithm is used: only
tool designers/programmers do.
Time wheel: simulation time goes in one direction
Timescales use two numbers: the reference
time unit and the precision.
The first number sets the unit of
measurements for times and delays.
The second sets the precision, that is, the
smallest unit of time that the simula
always and initial Blocks
Combinational or Sequential
Similar in syntax, but initial blocks only run
one time. always blocks run continuously
and are updated whenever something in
their sensitivity list changes.
All blocks run in parallel.
Sun workstations may be accessed remotely in the open computing lab (JD1622C) via Hummingbird. Directions are available from computer support (JD 1109 or 1112) and will be available on the course web site.
Turn em OFF!
`timescale Directive ECE 526
Compiler Directives Timescales use two numbers: the reference time unit and the precision. The first number sets the unit of first number sets the unit of measurements for times and delays. The second sets the precisi
Initial isnt Physical
A B initial C = A & B; Then what? What happens when A or B changes? CLR initial OUT <= 1b0; Thats not how a flipflop works! C CLK RST D Q OUT A B
always is for circuits
C CLK always @(A or B) C = A & B; This is the way a ga
Synchronous design means that all registers are clocked by the same signal. Synchronous design is always desirable in design is always desirable in digital circuits. Not all events are synchronous.
ECE 526 Homework 1 Due February 4, 2010 1. Explain the limitations of using K-maps for logic design and minimization. 2. What are some factors that might cause one design to be better than another, assuming both are functionally correct? 3. What are two r
ECE 526 Homework 2 Due February 25 1. Code a Verilog module that will: Output 1 if preset is low and reset is high Output 0 if reset is low and preset is high Output an X if both preset and reset are low Toggle states on the clock rising edge if both pres
Verify the Hierarchy
Enumerated Type Simulation
Enumerated type is an internal variable.
Output is one-hot binary.
Enumerated type is not a primary input or
output, so it does not appear in the test fixture.
Parameters in Package
Catalog Course Description
ECE526 Digital Design with Verilog and SystemVerilog
Digital Design with Verilog and
Prerequisite: ECE 320/L. Corequisite: ECE 526L. This course
covers the use of Verilog and SystemVerilog Languag
Constants, Sort of Constants
Previously used define macros to set
Parameters are similar.
Main syntactical differences is that
defined macros must have backtick (`)
before each instance and parameters do not.
Initial conditions: neither R nor S is asserted (both are
logic 1). Q and Q and unknown (Verilog X).
What happens if R = x, S = 0 and initial conditions (Q and
Q) are unknown?
Result: Q and Q stay X forever. ~(1 & X) = X.
Lab 6, Supply 0 and 1
Lab 6 calls for setting delays with Specify
This is not the normal and accepted use of
Their proper usage will be covered later, in
the modeling section.
Ignore delay specifications.