Diana Oboikovitz
TCP/IP
September 2, 2008
Homework # 1
Chapter 2 questions 1-5
1. How are the OSI and ISO related to each other?
The ISO is the International Standards Organization. It is a volunteer organization
dedicated to the worldwide agreement on st

Module #1 - Logic
1.2 Algebra of propositions
Compound propositions p and q that have
same truth values in all possible cases are
called logically equivalent, denoted as p
logically
denoted
q.
The symbol is not a logical connective, it
The
means that p q

Q1)
> A=[7 -3 -4; -3 6 -2; -4 -2 11]
A=
7 -3 -4
-3 6 -2
-4 -2 11
> b=[-11;3;25]
b=
-11
3
25
> x=inv(A)*b
x=
1.0000
2.0000
3.0000
Q2)
> t=0:0.1:10;
> v=15*(1-exp(-t/2);
> plot(t,v)
Voltage (V) Vs Time (s)
15
V o l t a g e (V )
10
5
0
0
1
2
3
4
5
Time (s)
Q

Module #1 - Logic
Chapter 1:
Logic
Text Book: Sections 1.1 1.3
11/16/13
(c)2001-2003, Michael P. Frank
1
Module #1 - Logic
Section 1.1: Truth Tables
Mathematical Logic is a tool for working with
complicated <compound statements>. It includes:
A language

Equipment
.Escort Digital Multimeter
.DC Power Supply
.Resistor Network Board
Decade resistance box
Procedure
Part A: Thevenins Equivalent Circuit
Build the circuit shown in figure 2 on the circuit board. Set the power supplys CH2 to 15 V and
connect it a

Department of Mathematics & Statistics
MTH 221: Linear Algebra
Course Policy and Syllabus Spring 2012
Course Description (catalog):
Covers systems of linear equation, algebra of matrices, linear transformations, determinants,
vector spaces, inner product

Rizwan Bakhsh
Assignment HW 6 due 05/24/2012 at 05:59pm GST
ft-aus-mth221
(incorrect)
1. (1 pt) Let V be a vector space, and T : V V a linear transformation such that T (5v1 + 3v2 ) = 2v1 5v2 and
T (3v1 + 2v2 ) = 2v1 2v2 .
4. (1 pt) Find the matrix A of t

A
Course Title
& Number
B
Pre/Corequisite(s)
C
Number of
credits
D
Faculty Name
E
Term/ Year
F
MTH 213 - Discrete Mathematics
MTH 103 or MTH 102
Sections
3
Padmapani Seneviratne
Fall 2013
Instructor
Information
Course
Day
s
Time
Location
10169
G
CRN
MTH21

American University of Sharjah
Department of Mathematics & Statistics
MTH 213
Discrete Mathematics
Pani Seneviratne
Slides modified from Dr. Michael P.
Franks Discrete Math course slides.
11/16/13
(c)2001-2003, Michael P. Frank
1
Course Overview
11/16/13

COMMUNICATIONS NETWORKS
T. Landolsi
Course Policies
AUS policies strictly enforced
Homework assignments
Attendance is mandatory
Any form of cheating results in F grade
Plagiarism in project report will be severely penalized
Cell phones are prohibited duri

V CC
5V
S1
U 1A
7404N
Key = A
X1
U3A
7408N
U2B
U3B
7404N
2.5 V
U4A
7408N
7432N
S2
Key = B
2b is the below one [2a is the one up ^]
V CC
5V
S1
U1A
7404N
Key = A
7408N
U2B
U3B
7404N
7408N
S2
Key = B
3)
X1
U3A
U4A
7432N
2.5 V
V CC
5V
S1
U 1A
7404N
Key = A
X1

Q1)
Network layer deals with IP addresses, which is responsible to take data from one host to
another. While, Transport layer deals with Ports, they are logical address within a host, which
tells the host to which application this data belongs to.
Q2)
A p

American University of Sharjah
COE370
Homework Assignment2
1. [25pts]Determinetheabsoluteandsignificantbandwidthsofthefollowingsignals:
a. s1(t ) = 107 + 2 cos(36p 103 t )
b. s2 (t ) = 3 + sin(6p 103 t + p / 4) + cos(6p 103 t + p / 4)
c.
s 3 (t ) = sin

Course 3: Digital encoding of the
baseband signals
1
Soon it's all going to be digital
anyway. It's all going to be saved
on a little coin somewhere.
Richard Donner
(Supermans creator)
2
Agenda
Transmission types
Digital signals
Key terms
Objectives of th

COE221: Digital Systems
Fall 2012
American University of Sharjah
Homework #5
Important Dates:
Homework due date is posted on iLearn Announcements
Homework Info: (From Manos Book - 5th Edition)
1) Problem 5.2
2) Problem 5.6
3) Problem 5.8
4) Problem 5.9
5)

COE221: Digital Systems
Fall 2012
American University of Sharjah
Homework #4
Important Dates:
Homework due date is posted on iLearn Announcements
Homework Info: (From Manos Book - 5th Edition)
1) Problem 4.5
2) Problem 4.15
3) Problem 4.26
4) Problem 4.28

Conclusion
In this lab we verified the function of a negative edged and positive edged D-Flip Flop. We also
learnt how to draw timing diagrams using the given inputs. Furthermore, we used a different way
to use the JK Flip Flop, as a D Flip Flop. Lastly,

Lab Equipments and Circuit Components
1. Equipment
LT345 Logic Tutor Board
Power Supply
2. Circuit Components
IC Type 74279 Quad S-R latches
IC Type 7475 Quad gated D-latches
IC Type 7474 Dual positive edge-triggered D flip-flops
IC Type 7476 Dual negativ

Instructor: Dr. Fadi Aloul
Lab Instructors:
Mr. Suresh Radder (Sec 1)
Office: EB2-126A
Email: sradder@aus.edu
Ms. Praveena Kolli(Sec 2,3,4 )
Email:pkolli@aus.edu
Office: LIB-022H
Semester: Fall 2012
American University of Sharjah
College of Engineering
Co