CSCI 401 Test 1
Dr. Keith Evan Schubert
1. You are the project lead at Micro Performance. The company wants you to select
which option would be best for their new Micro Speed processor.
(a) Speed up clock
CSCI 401 TEST 2 PRACTICE
(1) Given a non-pipelined architecture running at 2.5GHz, that takes 5 cycle to nish an instruction.
You want to make it pipelined with 5 stages. The increase in hardware forces you to run the machine
at 2GHz. The on
CSCI 401 Final
1. (60 pts) You are given a 128-bit asynchronous bus with a time of ight of 10 ns.
Your computer has the following equipment attached:
Total Latency: 7.84 ms
Disk Transfer Rate: 100MB/s
Number of Disks: 4
Cache block size = 2offset bits = 25 bytes = 23 words = 8 words
Number of entries = 2index bits = 25 = 32 entries
Total bits = 32 lines x (1 valid bit + 22 tag bits + 8x32 data b