Ve 270 Introduction to Logic Design
Lab 3
Design of an SSD Driver
UM-SJTU Joint Institute
Shanghai Jiao Tong University
June 2013
1. Objective
To design a Seven-Segment Display (SSD) driver using Xilinx ISE, and to implement the circuit in an FPGA
chip.
2
Topic 1
Introduction to Digital Design
1
Why Study Digital Design?
Many elements of our lives are or are to
become digital
Computer, camera, cell phone, TV, car.
Electronic devices are made smaller and
smarter
Enabled by shrinking and more capable
chips
Topic 2
Basic Logic Gates
1
Electronic Switch Transistors
control
input
Transistors are the basis of binary
digital circuits
Transistors operate at 2 values
H / L or
On / Off or
1/0
off
source
input
source
input
Evolution of electronic switches
1930s: R
Topic 3
Boolean Algebra & Optimization
Ve270 Introduction to Logic Design
1
Boolean Algebra
Traditional algebra
Variables represent real numbers
Operators operate on variables, return real numbers
Boolean Algebra
Developed mid-1800s by George Boole t
Topic 4
Combination Circuit
1
What is Combinational Circuit?
Combinational Circuit
A digital circuit whose output depends only upon the present
combination of its inputs
Output changes only when inputs change
Output changes once inputs change
As oppo
Ve270 Introduction to Logic Design
Lab 1
Design of a Full Adder
- A Tutorial on Xilinx ISE
UM-SJTU Joint Institute
Shanghai Jiao Tong University
May 2013
1. Objective
To become familiar with Xilinx Integrated System Environment (ISE) software for FPGA bas
Ve 270 Introduction to Logic Design
Lab 2
Design of a Multiplexed Datapath
UM-SJTU Joint Institute
Shanghai Jiao Tong University
May 2013
1. Objective
To design a simple datapath using multiplexer (MUX) in Xilinx ISE, and to implement the circuit in an
FP
Ve 270 Introduction to Logic Design
Lab 4
Design of a Counter
UM-SJTU Joint Institute
Shanghai Jiao Tong University
June 2013
1. Objective
To understand and design a special FSM Counter.
To integrate an FSM with a combinational circuit.
2. Requirement
In
Ve 270 Introduction to Logic Design
Lab 5
Design of a Counter
Modeling with Verilog HDL
UM-SJTU Joint Institute
Shanghai Jiao Tong University
July 2013
1. Objective
To model a digital circuit with HDL
To experience the development process of an FPGA based
Ve 270 Introduction to Logic Design
Lab 6
Design of a Clock Divider
UM-SJTU Joint Institute
Shanghai Jiao Tong University
July 2013
1. Objective
To get familiarized with binary counters.
To design a clock divider that slows down the frequency of a clock s
Ve 270 Introduction to Logic Design
Lab 7
Design of a Timer
UM-SJTU Joint Institute
Shanghai Jiao Tong University
July 2013
1. Objective
To design a two-digit timer that counts the number of seconds from 00 to 59, and repeats.
To display the two digits us
Ve 270 Introduction to Logic Design
Lab 8
Design of a Digital Device
UM-SJTU Joint Institute
Shanghai Jiao Tong University
July 2013
1. Objective
To design a digital system that
Rolls your student ID across the four SSDs on the FPGA board when the system
Topic 13
RTL Design
1
bi
bo
Combinational
logic
n1
Controllers (FSM)
s1
Describes behavior of circuits
Takes inputs, generates outputs
Implemented with state register and
combinational logic
Register
Controller and datapath
components working togethe
Topic 1
Introduction to Digital Design
1
Why Study Digital Design?
Many elements of our lives are or are to
become digital
Computer, camera, cell phone, TV, car.
Electronic devices are made smaller and
smarter
Enabled by shrinking and more capable
chips
Topic 2
Basic Logic Gates
1
Electronic Switch Transistors
control
input
Transistors are the basis of binary
digital circuits
Transistors operate at 2 values
H / L or
On / Off or
1/0
off
source
input
source
input
Evolution of electronic switches
1930s: R
Topic 3
Boolean Algebra & Optimization
Ve270 Introduction to Logic Design
1
Boolean Algebra
Traditional algebra
Variables represent real numbers
Operators operate on variables, return real numbers
Boolean Algebra
Developed mid-1800s by George Boole t
Topic 4
Combination Circuit
1
What is Combinational Circuit?
Combinational Circuit
A digital circuit whose output depends only upon the present
combination of its inputs
Output changes only when inputs change
Output changes once inputs change
As oppo
Topic 5
Karnaugh Map
Ve270 Introduction to Logic Design
1
Karnaugh Map (K-map) Technique
A graphical technique used to simplify a logic equation
A way to show the relationship between the logic inputs
and corresponding output
Like true table
Much clea
Topic 6
Latches and Flip Flops
1
Introduction
Beginning from this lecture, we will:
Design a new building blocks, latch & flip-flop, that store value of
a bit
Combine the blocks to build multi-bit storage a register
Describe the sequential behavior of
Topic 7
Finite State Machine
1
Describing Behavior of Sequential Circuit
Finite-State Machine (FSM)
A way to describe desired
behavior of a sequential circuit
Consists of a set of states,
transitions among states, and
maybe inputs and outputs
Outputs:
Topic 8
FSM Optimizations
1
Optimization by State Reduction
Goal: Reduce number of states in FSM without
changing behavior
Fewer states potentially reduce size of state register
Consider the two FSMs below with x=1, then 1, then 0, 0
Inputs: x; Outputs
Topic 9
Introduction to Verilog HDL
1
Reference
Advanced Digital Design with Verilog HDL, 2/e, Michael
Ciletti, 2010, ISBN: 978-0136019282
IEEE Standard for Verilog HDL, www.ieee.org
2
Hardware Description Language (HDL)
An HDL is a language that descr
Topic 10
Counters
1
Counters
Count up or count down
Count in different format: binary, decimal, one-hot,
Implemented with flip flops triggered by their clocks
Can be designed as an FSM
Counters:
Asynchronous counters
Synchronous counters
2
Asynchronous
Topic 11
Register & Shifter
1
Introduction
Two major subsystems in typical digital system
Controller
Controllers generates signals to control datapath based on environment event
or state
Datapath
Datapath routes data to particular destination device
Course Introduction
Ve270 Introduction to Logic Design
1
Course in CE Curriculum
Analog HW
Digital HW
Software
VE312
Physical layer of digital
design
VE270
Fundamental of Digital
HW
VE280
Programming in HLL
VE427
Physical layer of digital
system
VE370
uPr