Ve 270 Introduction to Logic Design
Lab 3
Design of an SSD Driver
UM-SJTU Joint Institute
Shanghai Jiao Tong University
June 2013
1. Objective
To design a Seven-Segment Display (SSD) driver using Xili
Topic 1
Introduction to Digital Design
1
Why Study Digital Design?
Many elements of our lives are or are to
become digital
Computer, camera, cell phone, TV, car.
Electronic devices are made smaller a
Topic 2
Basic Logic Gates
1
Electronic Switch Transistors
control
input
Transistors are the basis of binary
digital circuits
Transistors operate at 2 values
H / L or
On / Off or
1/0
off
source
input
Topic 4
Combination Circuit
1
What is Combinational Circuit?
Combinational Circuit
A digital circuit whose output depends only upon the present
combination of its inputs
Output changes only when in
Ve270 Introduction to Logic Design
Lab 1
Design of a Full Adder
- A Tutorial on Xilinx ISE
UM-SJTU Joint Institute
Shanghai Jiao Tong University
May 2013
1. Objective
To become familiar with Xilinx In
Ve 270 Introduction to Logic Design
Lab 2
Design of a Multiplexed Datapath
UM-SJTU Joint Institute
Shanghai Jiao Tong University
May 2013
1. Objective
To design a simple datapath using multiplexer (MU
Ve 270 Introduction to Logic Design
Lab 4
Design of a Counter
UM-SJTU Joint Institute
Shanghai Jiao Tong University
June 2013
1. Objective
To understand and design a special FSM Counter.
To integrate
Ve 270 Introduction to Logic Design
Lab 5
Design of a Counter
Modeling with Verilog HDL
UM-SJTU Joint Institute
Shanghai Jiao Tong University
July 2013
1. Objective
To model a digital circuit with HDL
Ve 270 Introduction to Logic Design
Lab 6
Design of a Clock Divider
UM-SJTU Joint Institute
Shanghai Jiao Tong University
July 2013
1. Objective
To get familiarized with binary counters.
To design a c
Ve 270 Introduction to Logic Design
Lab 7
Design of a Timer
UM-SJTU Joint Institute
Shanghai Jiao Tong University
July 2013
1. Objective
To design a two-digit timer that counts the number of seconds f
Ve 270 Introduction to Logic Design
Lab 8
Design of a Digital Device
UM-SJTU Joint Institute
Shanghai Jiao Tong University
July 2013
1. Objective
To design a digital system that
Rolls your student ID
Topic 13
RTL Design
1
bi
bo
Combinational
logic
n1
Controllers (FSM)
s1
Describes behavior of circuits
Takes inputs, generates outputs
Implemented with state register and
combinational logic
Regis
Topic 1
Introduction to Digital Design
1
Why Study Digital Design?
Many elements of our lives are or are to
become digital
Computer, camera, cell phone, TV, car.
Electronic devices are made smaller a
Topic 2
Basic Logic Gates
1
Electronic Switch Transistors
control
input
Transistors are the basis of binary
digital circuits
Transistors operate at 2 values
H / L or
On / Off or
1/0
off
source
input
Topic 4
Combination Circuit
1
What is Combinational Circuit?
Combinational Circuit
A digital circuit whose output depends only upon the present
combination of its inputs
Output changes only when in
Topic 5
Karnaugh Map
Ve270 Introduction to Logic Design
1
Karnaugh Map (K-map) Technique
A graphical technique used to simplify a logic equation
A way to show the relationship between the logic inpu
Topic 6
Latches and Flip Flops
1
Introduction
Beginning from this lecture, we will:
Design a new building blocks, latch & flip-flop, that store value of
a bit
Combine the blocks to build multi-bit
Topic 7
Finite State Machine
1
Describing Behavior of Sequential Circuit
Finite-State Machine (FSM)
A way to describe desired
behavior of a sequential circuit
Consists of a set of states,
transitio
Topic 8
FSM Optimizations
1
Optimization by State Reduction
Goal: Reduce number of states in FSM without
changing behavior
Fewer states potentially reduce size of state register
Consider the two FS
Topic 9
Introduction to Verilog HDL
1
Reference
Advanced Digital Design with Verilog HDL, 2/e, Michael
Ciletti, 2010, ISBN: 978-0136019282
IEEE Standard for Verilog HDL, www.ieee.org
2
Hardware Desc
Topic 10
Counters
1
Counters
Count up or count down
Count in different format: binary, decimal, one-hot,
Implemented with flip flops triggered by their clocks
Can be designed as an FSM
Counters:
Asy
Topic 11
Register & Shifter
1
Introduction
Two major subsystems in typical digital system
Controller
Controllers generates signals to control datapath based on environment event
or state
Datapath
Course Introduction
Ve270 Introduction to Logic Design
1
Course in CE Curriculum
Analog HW
Digital HW
Software
VE312
Physical layer of digital
design
VE270
Fundamental of Digital
HW
VE280
Programming