ALUs
ALUs
Lets talk about Arithmetic and Logic Units
(ALUs.)
A microprocessor is made up of many
components:
Central Processing Unit - Performs the data
manipulation tasks of the computer and
sequences each step in these tasks.
Arithmetic and Logic Un
Universal Properties of
NAND and NOR Gates
Boolean Algebra II
DeMorgans Law
a b a b
Dual of DeMorgans Law
a
a
b
b
Gate
Equivalency
a
b
a
b
a
b
a
b
Boolean Algebra II
Gate
Equivalency
a
b
Q:Why is this useful?
A:It allows us to build functions
using onl
Adders
Adders
Assume we wish to add two 1 bit binary
numbers and get a 2-bit result.
A,B = 1-Bit Operands
Result = COUT, Sum
A
0B
0B
1B
1B
B
0B
1B
0B
1B
B =>Binary Number
SUM
0B
1B
1B
0B
COUT
0B
0B
0B
1B
Rather than numerical variables think of these
Digital Logic Gates
Digital Logic Gates
There are three types of logic gates from
which we can build all digital computers.
Theyre all isomorphically related to
semantic logic operators
Consider:
Iff* Sally asks John AND John accepts, then
theyll go out
Decoders
Decoders
Starting w/ the decoder/demux function
definition, lets design a decoder/demux.
1:2 Y0
DeMux
G
Y
S0
1
G
G
G
S0
Y0
Y1
0
1
G
0
0
G
By inspection:
Y0 S 0 G
Y1 S 0 G
Decoders
Lets build the decoder/demux using
AND/OR logic. Y0 S 0 G Y1 S 0
Boolean Algebra I
Boolean Algebra I
Debugging circuits:
You will be building circuits in the labs which
will not work as you wish.
Tips
Complete the truth table for the function
Apply all combinations to see if ckt responds OK
For erroneous output t
EEE 120
Sam Gay
Sam Gay
EEE120
Lab: Simulation 3 (Stage C)
Date Created: 03/03/2015
Date Due: 03/12/2015
Pg. 1 of #
EEE 120
Sam Gay
Objective:
Blah blah blah
Expected Results:
Blah blah blah
Discussion:
Circuits (images and truth tables)
Summary
Results
N
EEE 120
Sam Gay
Sam Gay
EEE120
Lab: Simulation 2 (Stage B)
Date Created: 02/19/2015
Date Due: 02/26/2015
Course #: 28239
Pg. 1 of 8
EEE 120
Sam Gay
Objective:
Continue practicing and improving skills with LogicWorks
Become familiar with implementation of
EEE 120
Sam Gay
Simulation Lab 1 (Part A)
Sam Gay
EEE 120
Lab: Simulation 1 (Stage A)
Date Created: 02/17/2015
Date Due: 02/19/2015
Pg. 1 of 6
EEE 120
Sam Gay
Objective:
Become familiar with LogicWorks and the Boolean gates (AND, OR, NAND, NOR)
Use LogicW
Flip Flops
Flip Flops
We started by looking at(asynchronous)latches.
A latch with synchronizing input we called a
flip flop.
So far weve looked at two types of flip flops.
S
Q
Clk
RS
Flip Flop
R
Q
Truth Table for
RS Flip Flop
S
0
0
1
1
R
0
1
0
1
Q+
Q
0
Karnaugh Maps & POS
Karnaugh Maps & POS
Using Karnaugh Maps to minimize
functions by grouping 1s gave a Min SOP
Form.
Using Karnaugh Maps to minimize
functions by grouping 0s gives a Min POS
Form.
Karnaugh Maps & POS
The dual of the Uniting theorem is
Latches
Latches
Combinational Logic Circuits:
Present State (output) depends
only on present value of the
inputs.
Sequential Circuits:
Present State depends on
the present input AND
previous state.
R
S
Latches
Latch- a storage device with one input use
Final Exam
Closed Book, Closed Notes Individual Performance
More than 60% will cover
Implementing functions with PLDs, muxs and decoders.
Make sure you review problems from your last homework
Memory
Differences between ROM and RAM and their family. D
Synchronous Machines
Synchronous Machines
Any device that has memory and a
control/clock input is called a sequential
machine. Latches, flip-flops, and ripple
counters are examples of sequential
machines.
When devices are synchronized so that all
of the
Ripple Counters
Ripple Counters
Now that we have flip-flops for memory,
we can start to design more interesting
circuits.
The first circuit well design is an
asynchronous counter called a ripple
counter.
Defn: Counter - a sequential circuit that
goes t
PROM Based Synch Machines
PROM Based Synch Machines
The brain (controller) of the microprocessor
you are building is a synchronous machine.
Rather than using combinational logic to
realize the functions that drive the flip-flop
array, the controller use
PLDs
PLDs
There is a need to implement combinational
logic functions using a minimum amount of
hardware.
Were going to look at three ways of doing
this:
Multiplexers
Decoders
Programmable Logic Devices
Programmable Array Logic (PAL)
PROM
Programma
GOOD LUCK!
Practice Exam II
EEE/CSE 120
1. Convert the following numbers from the given base to the bases indicated. Write your final
answers in the space provided. Assume unsigned.
a) Decimal 65.75 to binary, and hex
ANSWER: binary: _
hex: _
b) Binary 1
Number Systems
Number Systems
Review the decimal number system.
Base (Radix) is 10 - symbols (0,1, . . 9) Digits
For Numbers GT 9, add more significant digits
in position to the left, e.g. 19>9.
Each position we understand to carry a weight.
MSD
Weigh
Multiplexers
Password_
Muxs
Y X
Mux
Motivation
Z
Mux
T
Multiplexer (Mux)-Routes
one of many inputs to one
output.
Decoder (Demultiplexer
DeMux)-Routes one input to one
of many outputs.
Decoder
Route to Device B
Route to Device A
Muxs
Starting w/ the Mux
Moore Machines
Moore Machines
The circuits weve looked at so far fall into the
following general schematic:
QB'
QB
Y' QA' Y QA
Y'
1
InputY
0
Combinational Logic
Y QA'
+5V
TB
0
TC
Clk
1
0
S
J Q QC
C C
K R Q QC'
+5V
+5V
C.L. Output
0
TB
S
J Q QB
C B
K R Q Q
Mealy Machines
Mealy Machines & Project
Recall the block diagram of a Moore machine.
Input
Combinational
Logic
Clock
Flip-Flop
Array
Combinational
Output
Logic
The output now
changes when the
INPUT changes! i.e.,
asynchronously!
The difference between a M
Karnaugh Maps & SOP
Karnaugh Maps & SOP
Karnaugh Map: A grid used to store truth table
data in an equivalent form.
A
0
0
1
1
B
0
1
0
1
F
1
0
1
0
A
B
B
B
A
0
0
1
A
1
1
0
1
0
F=B
Karnaugh Map Method: A visual method for
identifying adjacency groups of 1s