ECE 626
Midterm Examination
Febr. 15, 2012
Open book
1. The trackand-hold stage shown has an input sine wave 1V peak, 10 MHZ. The
clock freqpency is 50 MHZ. Sketch the output waveform assuming ideal opam
and switches. -
What practical advantages does the
ECE 626
MIDTERM EXAMINATION
Febr. 23, 2006
Open book, open notes
Design singleended stray-insensitive switched-capacitor (SC) stages
realizing the transfer function
- 4 + 32
H(z) = - -
l - z
with positive element values. Do this in the following steps:
(a
ECE 626
Midterm Examination
Febr. 13, 2013
Open book
1. Find the transfer function H(s) = Vo/Vin, as well as the input and output
impedances of the stage shown. What is 20, at dc? Why?
IC2
2. Find Voufz) for the circuit shown. Which switches need advanc
Gbor C. Temes
School of Electrical Engineering and
Computer Science
Oregon State University
[email protected]
1/57
Switched-Capacitor Circuit Techniques
ORIGIN :
"SC" replacing "R"; 1873, James Clerk Maxwell, "A TREATISE ON
ELECTRICITY AND MAGNETISM", P
Noise in Analog CMOS ICs
Gbor C. Temes
School of Electrical Engineering and
Computer Science
Oregon State University
March 2013
[email protected]
1/25
Noise = Unwanted Signal
Intrinsic (inherent) noise:
generated by random physical effects in the device
Nonideal Effects in SC circuits
Gabor C Temes
School of EECS
Oregon State University
Rev. 9/4/2011
[email protected]
Components and Nonidealities
Switches:
Nonzero on-resistance
Clock feedthrough / charge injection
Junction leakage, capacitance
Noise
Cap
Sample-and-Holds
David Johns and Ken Martin
University of Toronto
([email protected])
([email protected])
University of Toronto
slide 1 of 18
D.A. Johns, K. Martin, 1997
Sample-and-Hold Circuits
Also called track-and-hold circuits
Often need
Gbor C. Temes
School of Electrical Engineering and
Computer Science
Oregon State University
[email protected]
1/25
Noise
Intrinsic (inherent) noise:
generated by random physical effects in the devices.
Interference (environmental) noise:
coupled from
ECE 626 Project
Rishi Gupta
School of Electrical Engineering and
Computer Science
Oregon State University
Matlab
Fs=10MHz
DC gain=0db
Fp=0~1MHz
1.
Declare and analog filter. I set the cutoff to 5MHz (random choice).
[num,den]=butter(2,5e6,'low','s');
H=tf
Switched-R Tuning Technique for Gm-C Filters
Tao Wang
Advisor: Gabor C. Temes
2/22/2010
1/9
Outline
Highly-linear tunable Gm-cell
A 2nd order Gm-C filter with Switched-R tuning
Simulation result
Conclusion
2/9
Gm-cell with source degeneration
I
I
Iop
THERMAL NOISE ESTIMATION IN
SWITCHED-CAPACITOR CIRCUITS
Jos Silva and Gbor C. Temes
School of Electrical Engineering and
Computer Science
Oregon State University
12/21/2004
[email protected]
1/22
Outline
Thermal noise effects in an SC
integrator
Switch
Single-ended vs. Differential SC Circuits
Single Ended
Differential
Number of Caps
1 (Cs)
2 (Cd)
Max Signal
1Vpp
2Vpp
Max Power
V2/2
2V2
Thermal Noise
kT/Cs
2kT/Cd
V2Cs/(2kT)
V2Cd/(kT)
SNR
Conclusion: For the same SNR, Cd = Cs/2, so
total capacitance is s
suite
5 An
:and
cc to
3.5011,
ed in
lback
rcuit.
JBVCI,
It
Sec-12.3
Switched-Capacitor Amplifiers
425
33
32
51
Vin CH x yam
(a)
. V0
+
Wu on
V- + _ x
m 0CIH x I"(out Vout
(b) ' to
Figure 12.30 (a) Unity-gain sampler, (b) circuit of (a) in sampling mode
Finite Gain Effects in SC Circuits
Gabor C Temes
School of EECS
Oregon State University
Rev. 03/09/2013
[email protected]
Non-Idealities of an Op-Amp
DC offset voltage
Finite dc gain
Finite bandwidth
Nonzero output impedance
Noise
[email protected]
1/8
ESE 626
MIDTERM EXAMINATION
February 16, 2009
Open book, open notes
l.a. Find the charge delivered by the amplier during the two clock phases in the gain circuit
shown below if the load is negligible
b. Find the slew rate required if fs = 10 MHz, and 10%
ECE 626
MIDTERM EXAMINATION
February 15, 2010
Open book
1. For the SC stage shown, nd
I a. the transfer function H(z);
b. the frequency response.
C3 (132
|T I I
02 1
$2 C1 (cfw_31
2. a. Find the voltage V43) of the 8/11 stage shown during the sampling pha
ECE 626
MIDTERM EXAMINATION
February 14, 2011
Open book
In the circuit shown, all capacitors are of the same size. Find
a. the transfer function H (z) of the stage;
b. the poie and zero locations in the z-plane;
c. the dc gain of the stage;
d. the 3-dB fr
Noise
David Johns and Ken Martin
University of Toronto
([email protected])
([email protected])
University of Toronto
1 of 55
D. Johns, K. Martin, 1997
Interference Noise
Unwanted interaction between circuit and outside
world
May or may not b
Switched-Capacitor Circuits
David Johns and Ken Martin University of Toronto ([email protected]) ([email protected])
University of Toronto
1 of 60
D. Johns, K. Martin, 1997
Basic Building Blocks
Opamps Ideal opamps usually assumed. Important n
An Efficient and Accurate DC
Analysis Technique for SwitchedCapacitor Circuits
4/8/15
Gabor C. Temes
School of Electrical
Engineering and Computer
Science
Oregon State University
[email protected]
1/12
SC branch and DC model
4/8/15
[email protected]
Youngho Jung
012614
School of Electrical Engineering and Computer Science
Oregon State University
Procedure
Cadence simulation with given block diagram
Extract the each integrator output
Plot histogram in the Matlab by using hist
Block Diagram
Histogram o
Continuous-Time Filters
David Johns and Ken Martin University of Toronto ([email protected]) ([email protected])
University of Toronto
1 of 89
D. Johns, K. Martin, 1997
Motivation
Switched-capacitor lters + Accurate transfer-functions + High l
ECE 626
Midterm Examination
Febr. 17, 2014
Open book
1. The S/H stage shown is realized in a technology with an: 0.05 m2/V.s and L =
0.1 pm. C = 1 [JP Assuming that the channel charge .9 divides equally at cut
off, find
a. the maximum allowable q such tha