17.3 The circuits of fig. 17.31 have been fabricated with a longer than expected gate
oxidation cycle. If the threshold voltages are still equal to the desirable value, sketch
V and compare the results to the target case.
1) In the circuit of Fig. 14.8 assume
(a) What is the minimum value of
(b) Determine the value of
gm 1=gm 2 =g m 3=( 200 )1
R D that ensures oscillation?
C L for an oscillation frequency of 1GHz and a total
low-frequency loop gain of 16.
In the circuits of Fig. 13.6, W/L = 20/0.5 and I=0.5mA. Calculate the harmonic
distortion in each circuit if the input signal has a peak amplitude of 100mV. How do
the results change if we double W/L or I?
Problem 13. 12
As illustrated in fig. 15.45 mismatches between the UP and DOWN currents translate to
phase offset at the input of a CPPLL. With the aid of the waveforms in Fig.15.45, calculate
the phase offset in terms of current mismatch.