EE3193: Introduction to VLSI Circuit
Spring 2014
Homework 1
Due: February 13th, 2014
1. Sketch a transistor-level schematic for a CMOS 3-input OR gate.
2. Sketch a transistor-level schematic for the following function:
.
3. Sketch a transistor-level sc
EE3193/EL5473 Intro. to VLSI
Homework Assignment 1
Due beginning of class September 15
1. Based on the evolutionary trends described in chapter 1, predict the integration
complexity and the clock speed of a microprocessor in the year 2015.
2. (Problem 1.5
EE3193/EL5473 Intro. to VLSI
Homework Assignment 1
Solution
1. Based on the evolutionary trends described in chapter 1, predict the integration
complexity and the clock speed of a microprocessor in the year 2015.
Year
82
85
89
93
97
99
Model
286
386
486
P
EE3193/EL5473 Intro. to VLSI
Homework Assignment 4
Solution
1. (Based on problem 6.21 in text, requires Cadence) Use Cadence to simulate a
pseudo-nMOS inverter in which the pMOS transistor is half the width of the
nMOS transistor. What are the rising, fal
EL 5473 Introduction to VLSI Design Homework Assignment 2
Due beginning of Class February 9, 2010
1. (Problem 2.1 in text) Consider an nMOS transistor in a 0.6 m process with W/L= 4/2 (i.e., 1.2/0.6 m). In this process, the gate oxide thickness is 100 and
EE3193/EL5473 Intro. to VLSI
Homework Assignment 3
Solutions
1. Sketch a 3-input AND-OR-INVERT (AOI) gate with transistor widths chosen to
approximate the effective rise and fall resistances equal to a unit inverter.
Compute the rising and falling propaga
EL 5473 Introduction to VLSI Design
Due beginning of Class March 27, 2010
1. (Problem 4.10 in text) Consider the two designs of a 2-input AND gate shown below. Give an intuitive argument about which will be faster. Back up your argument with a calculation
Design alternatives for barrel shifters
Matthew R. Pillmeier
Rushmore Processor 2
Unisys Corporation
Blue Bell, PA 19424
Michael J. Schulte and E. George Walters III
Computer Architecture and Arithmetic Laboratory
Computer Science and Engineering Departme
The 2004 IEEE Asia-Pacific Conference on
Circuits and Systems, December 6-9,2004
Design of a Novel Radix-4 Booth Multiplier
Hsin-Lei Lin, Robert C. Chang, Ming-Tsai Chan
Departmenf of Electrical Engineering,
National Chung Hsing University, Taichung, Taiw
<Undergraduate Thesis: EEE-2007-01-48>
Design of MIPS Processor Supporting
MAC with FPGA
Munju Lee, Taewoo Han
School of Electrical and Electronic Engineering
College of Engineering
-i-
Yonsei University
<Undergraduate Thesis: EEE-2007-01-48>
Design of MI
Parallel architecture modified Booth multiplier
A.R. C ooper, MSc, PhD
I ndexing terms: Circuit theory and design, Array processing, Digital arithmetic, Algorithms
Abstract: T he paper describes a novel implementation of the modified Booth algorithm in wh
EE3193/EL5473 Intro. to VLSI
Lab Session 1
Before starting the lab itself, complete Tutorial 1 you may want a TA to check that it
has been completed successfully.
1. Design a 3-input NAND gate including transistor sizing and draw your schematic
using Cade
EE3193/EL5473 Intro. to VLSI
Lab Session 4
Before starting the lab itself, complete Tutorial 4.
* Tutorials are found at: http:/eeweb.poly.edu/labs/nanovlsi/tutorials/CustomICTut.htm
1. Run simulations verifying the DLATCH schematic and extracted views cr
EE3193/EL5473 Intro. to VLSI
Lab Session 3
Before starting the lab itself, complete Tutorial 3 and you may even want the TA to
check off that it has been completed successfully.
* Tutorials are found at: http:/eeweb.poly.edu/labs/nanovlsi/tutorials/Custom
EE3193/EL5473 Intro. to VLSI
Lab Session 2
Before starting the lab itself, complete Tutorial 2 and you may want the TA to check off
that it has been completed successfully.
* Tutorials are found at: http:/eeweb.poly.edu/labs/nanovlsi/tutorials/CustomICTut
EE3193/EL5473 Intro. to VLSI
Homework Assignment 4
Due beginning of class November 24
1. (Based on problem 6.21 in text, requires Cadence) Use Cadence to simulate a
pseudo-nMOS inverter in which the pMOS transistor is half the width of the
nMOS transistor
EE3193/EL5473 Intro. to VLSI
Homework Assignment 3
Due beginning of class Tuesday, October 20
1. Sketch a 3-input AND-OR-INVERT (AOI) gate with transistor widths chosen to
approximate the effective rise and fall resistances equal to a unit inverter.
Compu
EE3193/EL5473 Intro. to VLSI
Homework Assignment 2
Solution
1. (Problem 2.1 in text) Consider an nMOS transistor in a 0.6 m process with W/L
= 4/2 (i.e., 1.2/0.6 m). In this process, the gate oxide thickness is 100 and
the mobility of electrons is 350 cm2
EE3193/EL5473 Intro. to VLSI
Homework Assignment 2
Due beginning of class September 29
1. Consider an nMOS transistor in a 0.25 m process with W/L = 8/2 (i.e., 1/0.25
m). In this process, assume the gate oxide thickness is 50 and the mobility of
electrons
VLSI Design, 2002 Vol. 14 (4), pp. 315327
A Fast ALU Design in CMOS for Low Voltage Operation
A. SRIVASTAVA* and D. GOVINDARAJAN
Department of Electrical and Computer Engineering, Louisiana State University, Baton Rouge, LA 70803-5901, USA
(Received 6 Oct
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 45, NO. 12, DECEMBER 1998
1585
Systematic Design of High-Speed and
Low-Power Digit-Serial Multipliers
Yun-Nan Chang, Student Member, IEEE, Janardhan H. Satyanarayana,
ARITHMETIC LOGIC UNIT (ALU) DESIGN
USING RECONFIGURABLE
CMOS LOGIC
A Thesis
Submitted to the Graduate Faculty of the
Louisiana State University and
Agricultural and Mechanical College
in partial fulfillment of the
requirements for the degree of
Master of
Chapter 5
ARM
Organization and Implementation
ARM organization
A[31:0]
control
address register
Register file
P
C
2 read ports, 1 write port +
1 read, 1 write port reserved for
r15 (pc)
Barrel shifter shift or rotate
one operand for any number of
bits
AL
ECE 261 Project Presentation 2 8-bit Booth Multiplier
Eric Wang Federico Gonzalez Bryan Flemming Jep Barbour
1
Abstract
The purpose of this project is to create a 8 by 8 multiplier using Booths multiplication algorithm. The 8-bit multiplicand and 8-bit mu
Arithmetic and Control Components
for an Asynchronous System
A THESIS SUBMITTED TO THE UNIVERSITY OF MANCHESTER
FOR THE DEGREE OF DOCTOR OF PHILOSOPHY
IN THE FACULTY OF SCIENCE AND ENGINEERING
1997
Jianwei Liu
Department of Computer Science
Table of Conte
Xia et al. / J Zhejiang Univ Sci A 2009 10(7):1067-1074
1067
Journal of Zhejiang University SCIENCE A
ISSN 1673-565X (Print); ISSN 1862-1775 (Online)
www.zju.edu.cn/jzus; www.springerlink.com
E-mail: jzus@zju.edu.cn
New method for high performance multipl