Cellular Communication Network- A review
Aman Gupta, 2012A3PS163P
Electrical & Electronics Department, BITS Pilani, India
f2012163@pilani.bits-pilani.ac.in
Abstract Telecommunication networks are one of the biggest
measures that define the technological a
SIGNALS
-Continuous
-Discrete
SYSTEMS
-Analog
-Digital
ADVANTAGES OF DIGITAL SYSTEMS
- Reproducibility of results
- Ease of design
- Programmability
- Speed
- Cost
- Integrated Circuits
DIGITAL CIRCUITS
- COMBINATIONAL
(Outputs depend only on present inpu
Quine-McCluskey Method
K-Maps Difficult in Visualization for
six variables and above
Not software adaptable
Quine-McCluskey Method
An Example
1. Find all the prime implicants
f (a, b, c, d ) m(0,1,2,5,6,7,8,9,10,14)
group 0
0 0000
group 1
1 0001
2 0010
8
IC CHARACTERSTICS
- Fan Out
- Propagation Delay
- Noise Margin
- Power Dissipation
2.4V
2.0V
0.8V
0.4V
Power Dissipation (PD)
Expressed
in Milliwatts
PD= VCC * ICC
ICC(avg)=(ICCH+ICCL)/2
Diminished Radix Complement
Number N in base r having n digits
(
Function with Dont care inputs
- Dont cares included while
computing Prime implicants
-In the Selection of Essential Prime
implicants dont cares not used.
Simplify Using QM Method
F(A,B,C,D) = (6,7,14)
d( A,B,C,D) = (0,8,15)
EX-OR Function
xy = xy + xy
EX
KARNAUGH MAPS
-Graphical
Device used to
Simplify Boolean expressions
-Relates
-Useful
inputs to Outputs
upto six variables
Row of a Truth Table corresponds
to a square in K-map
Adjacent square differ in only one variable
Combine squares with 1s
00
01
11
1
Hardware Description Language
(HDL)
Digital Design Flow
Behavior
RTL (Register Transfer Level)
Logic Circuit (Gates & FFs)
Layout
Abstractions in Digital IC
Design Example [1]
S=a+b+c
Co = Carry generated in the
above operation
Behavior
Abstractions in Di
Flip-Flops
Latches are transparent (=> any change
on the inputs is seen at the outputs
immediately).
This causes synchronization problems!
Solution: use latches to create flip-flops that
can respond (update) ONLY on SPECIFIC
times (instead of ANY time)
Digital Logic Families
ICs are also classified based on their specific
circuit technology, known as digital logic family.
Each family has its own basic electronic
components (NAND, NOR, and NOT gates), used
to build complex digital circuits.
Various di
Multiplication & Division Algorithms
Multiplication
Some general observations
1. Multiplication involves the generation of
partial products one for each digit in the
multiplier.
2. Partial products are summed to produce
the final product.
3. Partial produ
Algorithmic State Machines
(ASM)
Binary information in Digital Systems:
Data
Control
Data processing tasks:
Addition, decoding, counting etc
Control information provides command signals
monitoring data processing tasks.
Various modules are interconnected
PROGRAMMABLE
LOGIC
DEVICES
PLA Example
Implement the two functions:
F1=(0,1,2,4)
F2= (0,5,6,7)
Using a PLA of size 3x4x2
PROGRAMMABLE
ARRAY
LOGIC
Programmable Array Logic
(PAL)
OR plane (array) is fixed, AND plane can
be programmed
Less flexible than PL
BINARY MULTIPLIER
To Multiply two unsigned binary numbers.
Sequential Multiplier
Uses one adder and a shift register.
Initially Multiplier in Q and Multiplicand in B
With S = 0 no action and circuit is in state T0
Multiplication process starts when
Field Programmable Gate Arrays
Field Programmable Gate Arrays (FPGAs)
- Field programmable gate array is a VLSI module that can be
programmed to implement a digital system consisting of tens of
thousands of gates.
A Field Programmable Gate Array (FPGA)
is
MEMORY HIERARCHY
REG
CACHE
MAIN
SECONDARY
Memory Hierarchy
Registers
In CPU
Primary Memory
May include one or more levels of cache
RAM
Secondary memory
Magnetic/Optical
CACHE:
-High Speed Memory (SRAMs)
-Small in Size
-High cost
MAIN MEMORY
-High d
DIGITAL DESIGN
CS/EEE/INSTR F215
LAB TEST NOTICE
01/11/2013
The lab test for the above course will be conducted as per the following schedule:
SEC NO.1
FROM
2011B1A3799P
2011B4A3662P
2012A3PS172P
2012A7PS122P
SEC NO.2
FROM
2011A8PS319P
2012A3PS007P
2012A3
Electrical Science
Lecture-35-36: Magnetic Circuits
BITS Pilani
Pilani Campus
Dr. Navneet Gupta
Department of Electrical and Electronics Engineering
Magnetic Circuits
r
r
0
l
B
N
B
i
A 2 R
N
l
i
( N .i)
This is known as (mmf) magneto motive force (A T)
Electrical Science
Lecture-33-34: Polyphase Circuits
BITS Pilani
Pilani Campus
Dr. Navneet Gupta
Department of Electrical and Electronics Engineering
Recap
One can improve the power factor of a load by placing a
suitable reactance in parallel with the lo
Back to Combinational Logic Ckt design
DECODERS
D7
D0
A0
A1
A2
V
De Multiplexers
A De-multiplexer is a logic circuit that transmit
Information on a single line on one of 2n output
lines
Selection of output line depends on the value of
n select lines
A Dec
DESIGN OF CLOCKED
SEQUENTIAL CIRCUITS
DESIGN WITH UNUSED STATES
Design the circuit using D Flip Flops
Answer:
Da=ABx
Db=Cx+A+BCx
Dc=ABx+Cx+Ax
Y=Ax
The circuit is self correcting
STATE REDUCTION
STATE TABLE
Present
state
a
b
c
d
e
f
g
Next State
X=0
a
c
a
Electrical Science
Lecture-5: Topic- Nodal and Mesh analysis
Dr. Navneet Gupta
BITS Pilani
Pilani Campus
Department of Electrical and Electronics Engineering
Introduction: Nodal Analysis
Circuit analysis: The process by which we
determine a variable (eit
Electrical Science
Lecture-8: Maximum Power Transfer and
Superposition Theorem
BITS Pilani
Pilani Campus
Dr. Navneet Gupta
Department of Electrical and Electronics Engineering
MAXIMUM POWER TRANSFER
Courtesy of M.J. Renardson
http:/angelfire.com/ab3/mjram
Electrical Science
Lecture-11-12: Second order circuits
BITS Pilani
Pilani Campus
Dr. Navneet Gupta
Department of Electrical and Electronics Engineering
Lecture - 11
Second order circuits
SERIES RLC CIRCUIT
Consider series connected R, L, C circuit (sourc
Electrical Science
Lecture-6-7: Thevenins and Norton Theorem
Dr. Navneet Gupta
BITS Pilani
Pilani Campus
Department of Electrical and Electronics Engineering
from last Lecture
Find V0 using Mesh Analysis
Ans: 33/4 = 8.25 volt
Vx = 8 volt
BITS Pilani, Pila
Electrical Science
Lecture-9-10: Transient Response of circuits
BITS Pilani
Pilani Campus
Dr. Navneet Gupta
Department of Electrical and Electronics Engineering
from last lecture
Find the voltage v by employing the principle of
superposition
Dr. Navneet
Electrical Science
Lecture-1-4: Basic Elements and Laws
Dr. Navneet Gupta
BITS Pilani
Pilani Campus
Department of Electrical and Electronics Engineering
BITS Pilani
Pilani Campus
Course No. EEE F111
Lecture-1
The Course Handout
LECTURE-1:
Dr. Navneet Gupt
Electrical Science
Lecture-13-15: Diodes
BITS Pilani
Pilani Campus
Dr. Navneet Gupta
Department of Electrical and Electronics Engineering
Lecture - 13
Introduction
Diode is a non-linear element.
Aim: circuit analysis with nonlinear circuits.
Electric c
Electrical Science
Lecture-24: Operational Amplifier (Op-Amp)
BITS Pilani
Pilani Campus
Dr. Navneet Gupta
Department of Electrical and Electronics Engineering
Introduction
An operational amplifier (op-amp) is a direct coupled high gain
amplifier
inverting
Electrical Science
Lecture-16-17: Clippers and Zener Diodes
BITS Pilani
Pilani Campus
Dr. Navneet Gupta
Department of Electrical and Electronics Engineering
Lecture: 16
Example:Clipper circuit
i1
i2
Assume D ON
i i1 i2
vs 3
vs
3
i
4.5 103
1000 2000 1000