ECSE 4220 VLSI Design Homework #1
Due: Feb. 1st in class
1. Given the data in the table for nMOS transistor with 2F = -0.6V and
=k(W/L) where k=100uA/V2, a. Calculate VT0, W/L, and . b. If Vgs=2.0V,
1.
a) 1:1:1
b) 1:2:3
2. a) CDAB, DCBA
b) AD/BC (Solve same as part a)
3. We need to compare the average number of wires that switch from 0 to 1.
Without using bit inverting, switching probability at e
ECSE 4220 VLSI Design Project #2: Adder Design
Due: May 15, 2015 by emailing the report to TA Sneha Banerjee at [email protected]
Adder is one of the most fundamental building blocks in VLSI
ECSE 4220 VLSI Design Homework #4
Due: April 12 in class 1. Analyze the circuit as shown in Figure 1 and explain its functionality.
Figure 1: 2. Consider the circuit as shown in Figure 2, assume that
ECSE 4220 VLSI Design Homework #4
Due: Monday November 11 in class
1. Consider the three inverters in Fig. 1 that share the same input. The relative sizing of the
transistors are shown in Fig.1. Let P
ECSE 4220 VLSI Design Homework #1
Due: September 19th in class
1. Given the circuit below, label the Source and Drain of each transistor.
2. (2.2 in the textbook) Show that the current through two tra
ECSE 4220 VLSI Term Project #2: Ring Oscillator Design
Due: December 10th, 5PM by emailing the report in PDF format to [email protected]
1 Background
The ring oscillator is a de facto standar
ECSE 4220 VLSI Design Homework #3
Due: Feb. 22 in class 1. To design the NAND of four inputs with the input capacitance of C and the load capacitance of 18C, we have three different design styles as s
ECSE 4220 VLSI Design Homework #2
Due: Feb. 15 in class 1. Design an complementary static CMOS circuit with minimized number of transistors to realize the Boolean function: F=AB+CA, and assign the rel
VLSI Term Project 1: Inverter Design
October 28, 2013
David Hedin
For this project we were assigned to design an inverter using Cadence IC design software to
compare our ideal assumptions of an invert
Rensselaer Polytechnic Institute ECSE-4220 VLSI Design Final Sample Questions
1. Analyze the multiple-output dynamic logic circuit shown in Figure 1 and write out the function F1, F2, and F3.
Clk A
ECSE 4220 VLSI Design Homework #2
Due: September 26th in class
1. Sketch a transistor-level schematic of F=(A+BC+DE) and determine the relative sizing of all
the transistors to equalize the rise/fall
ECSE 4220 VLSI Design Homework #6
Due: December 2nd in class
1. Consider the D-FF and input waveform in Fig. 1. Describe the function of this D-FF and
draw the corresponding waveform of the output Q.
ECSE 4220 VLSI Design Homework #7
Due: May 5 in class
1. Given the true single-phased D-FF shown in Fig. 1, determine whether it is a positive or
negative triggered D-FF.
Figure 1: .
2. Design a 11-tr
ECSE 4220 VLSI Design Homework #2
Due: Friday Feb. 20th in class
1. (5 points) Sketch a transistor-level schematic of F=(A+BC+D) and determine the relative sizing
of all the transistors to equalize th
VLSI Term Project 1: Inverter Design
October 28, 2013
David Hedin
For this project we were assigned to design an inverter using Cadence IC design software to
compare our ideal assumptions of an invert
VLSI Term Project 2: Ring Oscillator
December 10, 2013
David Hedin
A ring oscillator is a simple loop of an odd number of inverters used to create a simple clock
signal. Using the delay of several inv
ECSE 4220 VLSI Term Project #1: Tutorial Write-Up Assignment
Due: April 7, 2015 by emailing the report to TA Sneha Banerjee at [email protected]
In order to assess your ability to operate CA
VLSI Term Project 2: Ring Oscillator
December 10, 2013
David Hedin
A ring oscillator is a simple loop of an odd number of inverters used to create a simple clock
signal. Using the delay of several inv
ECSE 4220 VLSI Design Homework #1
Due: Feb. 13th in class
1. (4 points) Given the circuit below, label the Source and Drain of each transistor.
Vdd
2. (2.2 in the textbook) (5 points) Show that the cu
ECSE 4220 VLSI Design Homework #1
Due: Monday Sept. 18th in class
1. (4 points) Given the circuit below, label the Source and Drain of each transistor.
Vdd
2. (5 points) Show that the current through