ECSE 4220 VLSI Design Homework #1
Due: Feb. 1st in class
1. Given the data in the table for nMOS transistor with 2F = -0.6V and
=k(W/L) where k=100uA/V2, a. Calculate VT0, W/L, and . b. If Vgs=2.0V, Vds=0.8V, and Vsb=0, what is the current Id and t

ECSE 4220 VLSI Design Homework #4
Due: Monday November 11 in class
1. Consider the three inverters in Fig. 1 that share the same input. The relative sizing of the
transistors are shown in Fig.1. Let P1 , P2 ,a nd P3 denote the dynamic power consumptions
o

ECSE 4220 VLSI Design Homework #1
Due: September 19th in class
1. Given the circuit below, label the Source and Drain of each transistor.
2. (2.2 in the textbook) Show that the current through two transistors in series is equal to the
current through a si

ECSE 4220 VLSI Design Homework #2
Due: September 26th in class
1. Sketch a transistor-level schematic of F=(A+BC+DE) and determine the relative sizing of all
the transistors to equalize the rise/fall time.
2. Sketch a transistor-level schematic and the la

VLSI Term Project 1: Inverter Design
October 28, 2013
David Hedin
For this project we were assigned to design an inverter using Cadence IC design software to
compare our ideal assumptions of an inverter circuit and a real world simulation. One pfet and on

ECSE 4220 VLSI Design Homework #3
Due: Feb. 22 in class 1. To design the NAND of four inputs with the input capacitance of C and the load capacitance of 18C, we have three different design styles as shown in Fig. 1. Estimate the shortest delay achiev

ECSE 4220 VLSI Design Homework #4
Due: April 12 in class 1. Analyze the circuit as shown in Figure 1 and explain its functionality.
Figure 1: 2. Consider the circuit as shown in Figure 2, assume that all inputs are initially 0 during the precharge p

ECSE 4220 VLSI Design Project #2: Adder Design
Due: May 15, 2015 by emailing the report to TA Sneha Banerjee at banerjeesneha1907@gmail.com
Adder is one of the most fundamental building blocks in VLSI systems. In this project you are to
implement one 1-bi

ECSE 4220 VLSI Design Homework #7
Due: May 5 in class
1. Given the true single-phased D-FF shown in Fig. 1, determine whether it is a positive or
negative triggered D-FF.
Figure 1: .
2. Design a 11-transistor true single-phased D-FF with the opposite cloc

ECSE 4220 VLSI Design Homework #2
Due: Friday Feb. 20th in class
1. (5 points) Sketch a transistor-level schematic of F=(A+BC+D) and determine the relative sizing
of all the transistors to equalize the rise/fall time when (a) un=2up, and (b) un=1.5up
2. (

ECSE 4220 VLSI Design Homework #1
Due: Feb. 13th in class
1. (4 points) Given the circuit below, label the Source and Drain of each transistor.
Vdd
2. (2.2 in the textbook) (5 points) Show that the current through two transistors in series is equal to
the

ECSE 4220 VLSI Design Homework #3
Due: Tuesday March 3rd in class
1. (5 points) Consider four designs of a 6-input AND gate shown in the following figure. Develop
an expression for the delay of each path if the path electrical effort is H. What design is

VLSI Term Project 1: Inverter Design
October 28, 2013
David Hedin
For this project we were assigned to design an inverter using Cadence IC design software to
compare our ideal assumptions of an inverter circuit and a real world simulation. One pfet and on

VLSI Term Project 2: Ring Oscillator
December 10, 2013
David Hedin
A ring oscillator is a simple loop of an odd number of inverters used to create a simple clock
signal. Using the delay of several inverters chained together, the output voltage oscillates

VLSI Term Project 2: Ring Oscillator
December 10, 2013
David Hedin
A ring oscillator is a simple loop of an odd number of inverters used to create a simple clock
signal. Using the delay of several inverters chained together, the output voltage oscillates

softwareVLSI Term Project 1: Inverter Design
October 28, 2013
David Hedin
For this project we were assigned to design an inverter using Cadence IC design software to
compare our ideal assumptions of an inverter circuit and a real world simulation. One pfe

Np cmos adder
True Single Phase clocked
The problem with this latch is that 1 and /1 might overlap, which
may cause two types of failures:
Node A can become undefined as it is driven by both D and B
when 1 and /1 are both high.
D can propagate through b

ECSE-4220 VLSI Design Course Syllabus
Fall 2013, 3 credits
Objective:
To introduce the basic concepts and techniques in CMOS circuit design.
To present the critical VLSI design issues in the very deep sub-micrometer era.
To provide experience designing

Q1. D captured at falling edge of clk 1 and appears at output on next rising edge of clk2
Q
Q2. D captured at rising edge of clk 1 and appears at output on next falling edge of clk2. Condition: Both
clocks should not be zero at the same time.
Q3.
Add an i

ECSE 4220 VLSI Design Homework #6
Due: December 2nd in class
1. Consider the D-FF and input waveform in Fig. 1. Describe the function of this D-FF and
draw the corresponding waveform of the output Q.
CLK1
CLK2
D
Q
CLK1
CLK2
CLK1
CLK2
D
Figure 1: .
2. Cons

ECSE 4220 VLSI Term Project #2: Ring Oscillator Design
Due: December 10th, 5PM by emailing the report in PDF format to erprachisharma24@gmail.com
1 Background
The ring oscillator is a de facto standard circuit for delay measurement. It also has many other