Lesson 33: Exercises
33.1 In the simplified state machine diagram of a computer system consisting of
IP, DP and Memory, where do you need to add the information to take care of
the situations arising out of the Interrupt and DMA requests from devices.
Lesson 19: Exercises
19.1 In mainframe systems, the Multi-user programming and Scarce-resource sharing
needs, apart from other reasons, had led to the Supervisor-User level isolation and
Protection features between the programs. How are these isolation an
Lesson 18: Exercises
18.1 Matching the bandwidths of two communicating elements such as Cache and
DRAM, through data bus widths, imply faster transfer and hence less penalty time. If
Cache has multi-word blocks,
(a) interpret the meaning of byte-organized
Lesson 14: Exercises
14.1 Though we have not considered the instruction set in detail, let us pay some
attention to the basic arithmetic functions, and the related number representations. In
the following assignments, we will consider the use of the Sign-
Questions for self assessment
Module 7-Lecture 1
1. What is the role of testing in VLSI design flow?
2. What are the basic differences between VLSI testing and classical testing philosophy?
3. What are the different types of tests that can be performed on
Lesson 15: Exercises
15.1 Which is likely to be more power-consuming than the other?
(a) volatile .vs. non-volatile
(b) semi-conductor memory .vs. magnetic-core memory
(c) static memory .vs. dynamic memory
15.2 Which is likely to be faster than the other?
Lesson 12: Exercises
12.1 The format of a double-operand instruction of a CPU is:
OP Code-Source Data-Destination Data
If 12 double-operand instructions and 30 single-operand instructions must be
implemented, and if the op-code field
Lesson 13: Exercises
13.1 The format of the micro-word of a 30-state micro-program controller of a
system consists of a 4-bit Test field, 5-bit Next-state field and a 7-bit
Output field. Given this information, what are your inferences about:
(a) the numb
Lesson 11: Exercises
11.1 Now that we have learned more of the inner details of a CPU, right down to the
level of its controller, we are possibly having the required amount of exposure to
venture further. Let us upgrade our earlier Freshman CPU specificat
Questions for self assessment
Module 10-Lecture 1
1. What is the basic philosophical difference between testing a sequential circuit compared
to combinational circuit?
2. Why is testing a sequential circuit considered more complex compared to combinationa
Lesson 10: Exercises
10.1 We are aware that connecting two Nand gates back-to-back results in an S R
latch. Discuss the result of connecting two Nor gates in a similar manner.
10.2 To the Nand gate with one of its inputs connected to its output, as sh
Lesson 8: Exercises
8.1 Develop the ASM chart of a master-slave S-R flip-flop.
8.2 Develop the ASM chart of a master-slave T- flip-flop.
8.3 In slight contrast with the master-slave principle is an edge-triggered one, by
which the output transition occurs
Lesson 9: Exercises
9.1 Explain the differences between the working of the logic systems implemented by the
following two ASM charts, in which the TEST condition = 1 for all the left link paths
out of the diagonal (decision) boxes, and is 0 for all the ri
Lesson 4: Exercises
4.1 Any system takes some inputs, and generates some outputs. If so, explain the
role of the states of a system, using the process of the paper-and-pencil
method of arithmetic computation, as an example.
4.2 As per von-Neumann architec
Lesson 17: Exercises
17.1 In a coin-tossing game Head wins - Tail loses is a perfect complementary
situation, under normal circumstances. Likewise, in CPU-Cache interaction
do Maximizing hit-ratio and Minimizing miss-penalty form a similar
Lesson 20: Exercises
20.1 (a) Consider that 20-bit logical addresses are getting mapped to 16-bit physical
addresses. Sketch the mappings given that the Pages, for different settings, are of
size: (i) 4 KB, (ii) 2 KB, and (iii) 1 KB.
(b) Using the above m
Lesson 29: Exercises
29.1 Based on whatever knowledge you have gathered about a computer
system, list all the hardware and software features that will contribute
towards a high data throughput.
29.2 It was stated that once a CPUs performance utilization h
Lesson 32: Exercises
32.1 In order to enhance the CPU-Memory interactions one solution is to have an
exclusive processor-memory bus, in which case communication with other
sub-systems is exclusively through one of the memories meant only for that
Lesson 30: Exercises
30.1 (i) Explain all those factors that contribute to higher data throughput in the
case of non-impact printers compared with impact printers.
(ii) What are the drawbacks in non-impact printing?
30.2 X- and Y-counters are used to loca
Lesson 27: Exercises
27.1 Consider the scenario of multiple requests on a single interrupt line. The
INTA acknowledge signal that winds through the multiple device interfaces
identifies the interrupting device that is electrically closest as the highest
Lesson 31: Exercises
31.1 It is said that priority resolution among competing devices, to decide on the
next bus mastership, can be carried out in parallel with a data transfer taking
place on a bus. If so, list and explain the need for the hardware and s
Lesson 28: Exercises
28.1 A DMA controller supports up to 4 channels over which devices may request
for DMA transfers.
(a) Assuming that only one device is connected to each channel, explain the
possible scenarios when more than one DMA request is in.
Lesson 25: Exercises
25.1 In most of the microcomputer peripheral chips, you will find a single register
called a COMMAND/ STATUS register for configuring the chip to carry out
the selected functions. That register will be accessed by CPU with a single
Lesson 26: Exercises
26.1 In the context of a DMA transfer over an 1-byte wide data bus, consider the
following two different scenarios. 1 KByte of data are being transferred
(a) as one block of 1 KB, or
(b) at the rate of 1 byte only after every DMA requ
Lesson 24: Exercises
24.1 Programmed I/O is implemented by first verifying the Ready status of a
device, by reading the Device Status Register, and then performing a data
transfer through Device Data Buffer. In this process, two registers are
Lesson 23: Exercises
23.1 Let us revisit the problem given in Ex. 22.1. In the context of the address
translation architecture and in order to handle the program of size specified
therein, making suitable assumptions about features or parameters not
Lesson 22: Exercises
22.1 Three different types of programs each of which is known to consist of 12
pages of code and 18 pages of data, are also known to require not more than 3
pages of stack space for their execution. If the system allocates 16 pages fo
Lesson 21: Exercises
21.1 Assume that a Write cycle had just preceded a Read cycle, which refers to
the same data. If a TLB Hit results, discuss all the conditions under which the
correct data will not be fetched.
21.2 In page replacements, the LRU (Least
Lesson 16: Exercises
16.1 A little-endian 16-bit CPU running a data processing program had to be replaced by
a big-endian CPU having similar capabilities. During the replacement, all changes
with regard to the program were taken care of. However the data
Lesson 3: Exercises
3.1 It is said that to handle the devices having different characteristics (such as speed,
data-format, signal-type, etc.,) appropriate device interfaces are included so that
we can come up with a standardized set of signal lines that