CSL 852, Computational Geometry: Practice Problems
The plane sweep technique and applications
1. Design a polyhedron (3 dimensional version of a polygon) such that guards placed at every vertex
may not be able to cover the entire interior.
2. Design an O(
CSL 852, Computational Geometry: Practice Problems
Arrangements and levels
1. A partition of S into two subsets S1 and S2 is called linearly separable if there is a line such that S1
lies on one side of the line and S2 on the other side.
(a) Give a tight
CSL 852, Computational Geometry: Practice Problems
Clustering point sets using quadtrees and applications
1. Let S = cfw_p1 , p2 . . . pn be a set of n points in the plane and let k be a positive integer.We would like
to cover all the points using k disk
CSL 852, Computational Geometry: Practice Problems
Range searching
1. For the 2d range search tree, we would like to modify the construction in the following way to save
space.
Instead of storing the points in every level, we will store the points in ever
CSL 852, Computational Geometry: Practice Problems
Voronoi diagram and delaunay triangulation
1. Prove the following about a set of points (no three are collinear and no four points are cocircular).
(i) The circumcircle of a delaunay triangle doesnt conta
CSL 852, Computational Geometry: Practice Problems
Randomized incremental construction and random sampling
1. Provide all details of how you will implement the gridbased approach to determine all pairs that are
closer than distance .
In a model that supp
CSL 852, Computational Geometry: Practice Problems
Lower bounds on algebraic tree model
1. Prove an (n log h) lower bound for the 2D maxima problem where n and h are the input and output
sizes respectively.
Hint: Use a construction similar to the convex h
CSL 852, Computational Geometry: Practice Problems
Introduction using basic visibility problems
1. Construct a polygon P and a placement of guards such that the guards can see every point on the
boundary of P but there is at least one point in the interio
CSL 852, Computational Geometry: Practice Problems
nets, VC dimension and applications
1. An sample of a range space S = (X, R) is a subset C X such that for any range r R, the
following property is satised
X r C r


X
C
Let us two color the e
CSL 852, Computational Geometry: Practice Problems
Convex hull dierent paradigms and quickhull
1. For a given set S of n points let CH(S) be the convex hull of S. Consider the linesegment si,i+1
connecting the consecutive boundary points i and i+1 and th
Lesson 33: Exercises
33.1 In the simplified state machine diagram of a computer system consisting of
IP, DP and Memory, where do you need to add the information to take care of
the situations arising out of the Interrupt and DMA requests from devices.
33.
Lesson 29: Exercises
29.1 Based on whatever knowledge you have gathered about a computer
system, list all the hardware and software features that will contribute
towards a high data throughput.
29.2 It was stated that once a CPUs performance utilization h
Lesson 32: Exercises
32.1 In order to enhance the CPUMemory interactions one solution is to have an
exclusive processormemory bus, in which case communication with other
subsystems is exclusively through one of the memories meant only for that
purpose.
Lesson 30: Exercises
30.1 (i) Explain all those factors that contribute to higher data throughput in the
case of nonimpact printers compared with impact printers.
(ii) What are the drawbacks in nonimpact printing?
30.2 X and Ycounters are used to loca
Lesson 27: Exercises
27.1 Consider the scenario of multiple requests on a single interrupt line. The
INTA acknowledge signal that winds through the multiple device interfaces
identifies the interrupting device that is electrically closest as the highest
p
Lesson 31: Exercises
31.1 It is said that priority resolution among competing devices, to decide on the
next bus mastership, can be carried out in parallel with a data transfer taking
place on a bus. If so, list and explain the need for the hardware and s
Lesson 28: Exercises
28.1 A DMA controller supports up to 4 channels over which devices may request
for DMA transfers.
(a) Assuming that only one device is connected to each channel, explain the
possible scenarios when more than one DMA request is in.
(b)
Lesson 25: Exercises
25.1 In most of the microcomputer peripheral chips, you will find a single register
called a COMMAND/ STATUS register for configuring the chip to carry out
the selected functions. That register will be accessed by CPU with a single
ad
Lesson 26: Exercises
26.1 In the context of a DMA transfer over an 1byte wide data bus, consider the
following two different scenarios. 1 KByte of data are being transferred
(a) as one block of 1 KB, or
(b) at the rate of 1 byte only after every DMA requ
Lesson 24: Exercises
24.1 Programmed I/O is implemented by first verifying the Ready status of a
device, by reading the Device Status Register, and then performing a data
transfer through Device Data Buffer. In this process, two registers are
involved. De
Lesson 23: Exercises
23.1 Let us revisit the problem given in Ex. 22.1. In the context of the address
translation architecture and in order to handle the program of size specified
therein, making suitable assumptions about features or parameters not
speci
Lesson 22: Exercises
22.1 Three different types of programs each of which is known to consist of 12
pages of code and 18 pages of data, are also known to require not more than 3
pages of stack space for their execution. If the system allocates 16 pages fo
Lesson 21: Exercises
21.1 Assume that a Write cycle had just preceded a Read cycle, which refers to
the same data. If a TLB Hit results, discuss all the conditions under which the
correct data will not be fetched.
21.2 In page replacements, the LRU (Least
Lesson 16: Exercises
16.1 A littleendian 16bit CPU running a data processing program had to be replaced by
a bigendian CPU having similar capabilities. During the replacement, all changes
with regard to the program were taken care of. However the data
Lesson 20: Exercises
20.1 (a) Consider that 20bit logical addresses are getting mapped to 16bit physical
addresses. Sketch the mappings given that the Pages, for different settings, are of
size: (i) 4 KB, (ii) 2 KB, and (iii) 1 KB.
(b) Using the above m
Lesson 17: Exercises
17.1 In a cointossing game Head wins  Tail loses is a perfect complementary
situation, under normal circumstances. Likewise, in CPUCache interaction
do Maximizing hitratio and Minimizing misspenalty form a similar
complementary p
Lesson 19: Exercises
19.1 In mainframe systems, the Multiuser programming and Scarceresource sharing
needs, apart from other reasons, had led to the SupervisorUser level isolation and
Protection features between the programs. How are these isolation an
Lesson 18: Exercises
18.1 Matching the bandwidths of two communicating elements such as Cache and
DRAM, through data bus widths, imply faster transfer and hence less penalty time. If
Cache has multiword blocks,
(a) interpret the meaning of byteorganized
Lesson 14: Exercises
14.1 Though we have not considered the instruction set in detail, let us pay some
attention to the basic arithmetic functions, and the related number representations. In
the following assignments, we will consider the use of the Sign
Questions for self assessment
Module 7Lecture 1
1. What is the role of testing in VLSI design flow?
2. What are the basic differences between VLSI testing and classical testing philosophy?
3. What are the different types of tests that can be performed on