Source Free RL Circuits
http:/172.16.1.41/vitcc/mod/resource/view.php?id=12930
Transient & Steady State Response
Transient Response
1. Switch Operation
Electrical circuits are connected to supply by closing the
switch and disconnected from the supply by o
Thevenins Theorem
Thevenins Theorem
Thevenins Theorem
Thevenins Theorem
Thevenins Theorem
Thevenins Theorem
Thevenins theorem states that a
linear twoterminal circuit can
be replaced by an equivalent
circuit consisting of a voltage
source VTh in series w
7197851617P
AID: 20556  03/07/2016
The circuit has no initial capacitor conditions so, i 0 0 and v 0 0 0
Now convert the circuit from time domain to sdomain
We have to convert the elements in the circuit from time domain to sdomain
Apply the Lapl
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AID: 20556  19/06/2016
Step 1 of 3
The current in an RLC circuit with second order differential equation is
d 2i
di
10 25i 0 . 1
2
dt
dt
di 0
The initial current conditions are i 0 7 A and
0
dt
Apply Laplace Transform to the equation (1)
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Step 1 of 3
The voltage response in second order differential equation of RLC circuit is
d 2v
dv
2 v 0. 1
2
dt
dt
dv 0
The initial voltage conditions is v 0 350 V and
0
dt
Apply the Laplace Transform to the equation
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From the circuit,
For t 0 sec, when the switch is at position A, the initial conditions for the voltage across
capacitor and current through inductor are:
V 0 2.5 4
Volts
V 0 10
And iL 0 0 Ampere
Applying KVL to the c
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AID: 20556  19/06/2016
Step 1 of 3
The voltage in an RLC circuit with second order differential equation is
d 2v
dv
3 2 15 12v 0. 1
dt
dt
dv 0
V
The initial voltage conditions v 0 0 and
6
dt
s
Apply the Laplace Transform to the equation (1)
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AID: 20556  07/09/2016
From the circuit,
For t 0 sec, when the switch is at position A, the initial conditions are: V 0 0 and
35
35
0.875 A
30 10 40
For t 0 sec, when the switch is in position B, we have a sourcefree RLC series circuit
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AID: 20556  15/07/2016
From the circuit,
For
, switch is closed. The inductor acts as short circuit and the capacitor acts as open
t0
circuit. The equivalent circuit is as shown in figure below.
From this figure, the initial conditions for
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AID: 20556  16/07/2016
From the circuit,
For t 0 sec, the switch is in position A, the inductor acts like a short circuit.
So, the initial conditions for the voltage across capacitor and current through inductor are:
Assume the initial volt
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AID: 20556  22/06/2016
Step 1 of 3
The step response of an RLC circuit is
d 2i
di
2 5i 30. 1
2
dt
dt
The initial current conditions is i 0 18 A and
di 0
dt
36 A/s
Apply the Laplace Transform to the equation (1)
2
di 0
30
s I s si 0
2
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AID: 20556  24/06/2016
Step 1 of 3
The RLC series circuit is applied with unit step voltage 8u t
Apply the Kirchhoffs voltage law (KVL) to the RLC series circuit
1
di
8u t Ri t idt L . 1
C
dt
The RLC circuit parameters is L 1 H, R 1 ohm, C
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AID: 20556  16/07/2016
From the circuit,
By combining the resistors 15ohms, 25ohms which are connected in series then, the
equivalent resistance of
ohms is 40ohms. The equivalent value of 40ohms is
15
25
connected in parallel with 60ohms re
7197851623P
AID: 20556  15/07/2016
From the circuit,
For
, switch is closed. The inductor acts as short circuit and the capacitor acts as open
t0
circuit. The equivalent circuit is shown in figure (a).
From figure (a), the initial conditions for this c
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AID: 20556  27/06/2016
The circuit initial capacitor current conditions are: i 0 0 and v 0 0 0
Now convert the circuit from time domain to sdomain
We have to convert the elements from time domain to sdomain
Apply the Laplace Transform
719785169P
AID: 20556  24/06/2016
The current response of an series RLC circuit is:
d 2i t
di t i t
L
R
15 (1)
2
dt
dt
C
Substitute 0.5 H for L, 4 Ohms for R and 0.2 F for C
Substitute the initial current conditions is: i 0 7.5 A and
0
di 0
dt
Ap
7197851618P
AID: 20556  04/07/2016
The circuit has initial capacitor conditions
For t 0 , v 0 vs 12 volts
We have to convert the elements in the circuit from time domain to sdomain
Now convert the circuit elements for t 0
The input supply voltage is:
VIT
UNIVERSITY
(Estd. u/s 3 of UGC Act 1956)
SCHOOL OF ELECTRICAL SCIENCES
MODEL QUESTION PAPER TERM END EXAMINATION (Winter 2008)
Discipline
Subject
: M.Tech. VLSI Design
: ASIC Design
Semester
: II
Max. Marks : 100
ANSWER ALL THE QUESTIONS
1. (a)Descri
ASIC Design
(WINTER 2008)
Homework #1
Due: January 7, 2009 @ 3:00 pm
Please Note: For this homework, you must:
Name all instantiated instances, whether they are submodules of your own creation or gate
primitives.
Use informative module/signal/port names
VIT
UNIVERSITY
(Estd. u/s 3 of UGC Act 1956)
SCHOOL OF ELECTRICAL SCIENCES
II Semester M.Tech VLSI Design
ASIC Design Winter 2008
Faculty incharge: S.Sivanantham, Assistant Professor (Senior)
Due: January 27, 2009 @ 4:00 pm
HomeAssignment#2
Question 1
Wh
ASIC DESIGN
Relational
<
>=
>
<=
A: Less Than
A: Greater Than or Equal to
A: Greater Than
A: Less Than or Equal to
Reduction
&
A: Reduction AND
~&
A: Reduction NAND

A: Reduction OR
~
A: Reduction NOR
^
A: Reduction XOR
~^ or ^~ A: Reduction XNOR
Logica
ECE 551  Digital System Design & Synthesis
A: upper left 2. Study sections 3.13.7.2, 3.7.5  3.11 of IEEE Std 13642001. Logic Values a. Give the four basic Verilog signal values and their meanings A: 0 A: 1 A: x A: z b. For normal logic gates, a z on a
ASIC DESIGN
Exercise 1  Logic Values, Data Types & Operators  With Answers
WINTER 2008
Variables
In Verilog, what are nets used for?
A: For structural connectivity
What are registers used for in Verilog?
A: As an abstraction of storage (May or may not b
VIT
UNIVERSITY
(Estd.u/s3ofUGCAct1956)
SCHOOLOFELECTRICALSCIENCES
Discipline
:M.Tech.VLSIDesign
Subject
:ASICDesign
Max.Marks :50
Semester:II
Exam. :CATI
Time :1Hrs.
Question 1
Describe the ASIC Design Flow. Name each step and give a brief description
ASIC Design
Exercise 2 Sections 2, 3, and 7 of IEEE Std 13642001
Winter 2008
Write in the answer at A: for each of the following questions
1. Study sections 2.1  2.6.1, 2.7  2.7.4 of IEEE Std 13642001.
Comments
a. Write the word Verilog using the two
ASIC Design
Exercise 1  Logic Values, Data Types & Operators
Winter 2008
Write in the answer at A: for each of the following questions and bring to the Fridays
class whether complete or not for use in the discussion.
Variables
In Verilog, what are nets u
3
Explain the following about Wire Load Models
a) What are Wire Load Models and how and when are they used ?
Solution:
Wireload model contains estimated delay information for nets like capacitance,
resistance etc. based on fanout. A wire load model is use
IEEE 1149.1 JTAG
Boundary Scan Standard
October 1, 2007
1
Purpose of Standard
Allow test instructions and test data to be serially
fed into a componentundertest (CUT).
Allows reading out of test results.
Allows RUNBIST command as an instruction.
JTAG
ENGIN112: Introduction to Electrical and Computer Engineering Fall 2003 Prof. Russell Tessier
Understanding Sequential Circuit Timing
Perhaps the two most distinguishing characteristics of a computer are its processor clock speed and the size of its main