Special Topics in Design Automation of Analog VLSI
EE 788

Winter 2013
Loss due to a fault
Exhaustive testing for
N= 25, M= 50
Requires 2*75 vectors &
10*9 years
For 1 s time per 1 vector
Bridging fault
Comb logic Seq logic
Delay fault
Special Topics in Design Automation of Analog VLSI
EE 788

Winter 2013
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Special Topics in Design Automation of Analog VLSI
EE 788

Winter 2013
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Special Topics in Design Automation of Analog VLSI
EE 788

Winter 2013
Programmable Logic Arrays (PLAs) and Programmable Array Logics (PALs)
Programmable
connections
Programmable
Nonprogrammable Programmable
In a PLA
In a PAL
Programmable
connections
in PLAs
PLA/PAL advantages
Ease in circuit implementation
(dont have to
Special Topics in Design Automation of Analog VLSI
EE 788

Winter 2013
Presently Professor of Electrical
Engineering and Computer Science,
Emerita, at the University of
Michigan
Lynn Conway Their design revolution was all about
simplicity. "We figured out how to remove tons of
unnecessary design rules and optimizations, so t
Special Topics in Design Automation of Analog VLSI
EE 788

Winter 2013
Controllability & Observability
indices
1. Choose the path with lowest
index to control/observe fast
and minimize testing time
SCOAP Algorithm :
6 indices defined
CC1(a), CC0(a), CO(a)
SC1(a), SC0(a), SO(a)
Fault grading , Fault simulation , Fault coverag
Special Topics in Design Automation of Analog VLSI
EE 788

Winter 2013
NATIONAL INSTITUTE OF TECHNOLOGY,TRICHY15
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
ONLINE QUIZ
SUBJECT:VLSI SYSTEMS
CLASS:III ECE.
1. Speed of NMOS is that of PMOS.
A. half
B. one third
C. double
D. triple
2. The layout design rules are com
Special Topics in Design Automation of Analog VLSI
EE 788

Winter 2013
Quiz for the session1 on ASIC design flow:
1. What does 16nm indicate in the name of the technology node?
a. Width of the transistor
b. Placement grid for wires
c. Channel length of the transistor
d. Minimum achievable spacing between cells
2. Which leve
Special Topics in Design Automation of Analog VLSI
EE 788

Winter 2013
EC310 Review problems Solution
Wireless section Practice
Intro to Communications Systems
1. Describe the main purpose of any communication system.
To get data from a Transmitter to a Receiver across some medium, even in the
presence of noise.
2. In music
Special Topics in Design Automation of Analog VLSI
EE 788

Winter 2013
Question 1. Consider the signal below on the left.
TimeDomain
Amplitude
(V) here.
Type
equation
15
Voltage (V)
10
FrequencyDomain
10
5
0
5
10
15
0
0.1
0.2
0.3
0.4
0.5
0.6
Time (s)
0.7
0.8
0.9
1
2
Frequency (MHz)
1) Write out the timedomain equation
Special Topics in Design Automation of Analog VLSI
EE 788

Winter 2013
Modulation
Lecture No. 18
Dr. Aoife Moloney
School of Electronics and Communications
Dublin Institute of Technology
Lecture No. 18: Modulation
Overview
This lecture will look at the following:
Modulation
Benefit of modulation
Digital modulation
Generi
Special Topics in Design Automation of Analog VLSI
EE 788

Winter 2013
Detection of Bandpass Signals in
AWGN Part I
Lecture No. 19
Dr. Aoife Moloney
School of Electronics and Communications
Dublin Institute of Technology
Lecture No. 19: Detection of Bandpass Signals in AWGN Part I
Overview
This lecture will look at the follo
Special Topics in Design Automation of Analog VLSI
EE 788

Winter 2013
Detection of Bandpass Signals in
AWGN Part III
Lecture No. 21
Dr. Aoife Moloney
School of Electronics and Communications
Dublin Institute of Technology
Lecture No. 21: Detection of Bandpass Signals in AWGN Part III
Overview
This lecture will look at the f
Special Topics in Design Automation of Analog VLSI
EE 788

Winter 2013
Sample Questions
Lecture No. 22
Dr. Aoife Moloney
School of Electronics and Communications
Dublin Institute of Technology
Lecture No. 23: Sample Questions
Overview
This lecture has looked at the following:
Sample questions on the detection of bandpass si
Special Topics in Design Automation of Analog VLSI
EE 788

Winter 2013
PASTE QUESTION PAPER HERE
Expt. No:
3
Date:
06082012
AIM:
To develop a matlab program to compute the Y bus and Z bus of a given
system and to carry out simulation of a symmetrical three phase short circuit on a
given power system.
INPUT:
Line Data:
Line
Special Topics in Design Automation of Analog VLSI
EE 788

Winter 2013
b=input('Enter the number of buses: ');% input no. buses
l=input('Enter the number of lines: ');%input no. of lines
i=zeros(b,b);
r=zeros(b,b);
y=zeros(b,b)
c=zeros(b,b);
vf=zeros(b);
ymod=zeros(b,b);
z=zeros(b,b);
ymod=zeros(b,b);
for p=1:1:l% for loop t
Special Topics in Design Automation of Analog VLSI
EE 788

Winter 2013
PASTE QUESTION PAPER HERE
Expt. No:
2
Date:
30072012
AIM:
To develop a matlab program to compute the admittance matrix for any given
system when the line admittances and line charging admittance values are given
and to compute modified admittance matrix
Special Topics in Design Automation of Analog VLSI
EE 788

Winter 2013
Lecture
FPGA/ASIC Technology
and Design flow
Lecture Plan
Program Information:
Program organization
Recommended literature
Introduction to ASIC/FPGA Design
Basic chip structure
Worldwide HighTech Industry
Chip design industry and main applications
Special Topics in Design Automation of Analog VLSI
EE 788

Winter 2013
Ain Shams University
Faculty of Engineering
CHEP COMM Program
COMM 471: Digital Circuit Design
Fall 2015
Dr. Sameh A. Ibrahim
Assignment 1
CMOS Inverter
1. For a minimum dimension (W=L=2m) CMOS inverter, determine VM, tpHL and tpHL.
Given that: VTHN = 1 V