Homework 1
ICS 331 Digital Logic and Microprocessors
Due: 10/8/14
Exercise 1
Recursion and Induction
Let the function f be recursively defined as:
f(0) = 00 for

Lab Assignment 8
ICS 331 Logic Design &
Microprocessors Fall 2014
Task
Completion Due: 11/18/14
ALU environment
Design a unit implementing the ALU environment from section 22.1.3 on page 326. The Add-Sub(32) unit

Lab Assignment 7
ICS 331 Logic Design & Microprocessors
Fall 2014
Completion Due: 11/06/14
Task 1
More on Adders
An n-bit conditional-sum adder (CSA) is defined as full adder for n=1 and for n = 2 k >1 recursively as
The oval box that is labeled by a 0 an

Lab Assignment 3
ICS 331 Logic Design & Microprocessors
Fall 2014
Completion Due: 9/25/14
Tasks
You are given a circuit that steps through the hexadecimal values from 0, 1, , F on a hex display. You are

Lab Assignment 10
ICS 331 Logic Design & Microprocessors
Fall 2014
Completion Due: 12/11/14
Single Cycle DLX implementation
The DLX implementation will include the following modules
a) ALU environment (complete the details, 22.1.3)
b) Shifter Environment

Lab Assignment 9
ICS 331 Logic Design & Microprocessors
Fall 2014
Completion Due: 11/21/14
Task 1
Counting Display
a) Use an 8-bit Register, an 8 bit adder, a clock signal and two hex disp

Lab Assignment 11
ICS 331 Logic Design & Microprocessors
Fall 2014
Completion Due: 12/11/14
Task 1
Implement the single cycle DLX datapath based on the circuit given in the Logisim Circuit
SingleCycleDLX. Add the ALUenv and SHIFTenv implementations from y

Name:_
Sample Final Exam
ICS 331 Digital Logic and Microprocessors
Question 1
Boolean Formulas
You are given formula h(X3,X2,X1) = X1*X2 + Not(X2)*X3 + Not(X1)*Not(X3)
a) Determine a SOP formula equivale

Sample Exam Questions
ICS 331 Digital Logic and Microprocessors
Question 1
Binary representation
The following lists part of algorithm BR from the book to calculate a binary representation

Lab Assignment 5
ICS 331 Logic Design & Microprocessors
Fall 2014
Completion Due: 10/14/14
In the following assignments, please follow the recommended register use
conventions from slide 14 of the Harris lecture notes, e.g. arguments are passed in
R4-R7,

Lab Assignment 6
ICS 331 Logic Design & Microprocessors
Fall 2014
Completion Due: 10/28/14
Tasks
Consider the Boolean Functions as defined by B[i](X[3:0]) = OUT[i] for i = 0.2 and:
<OUT[2:0]> = <(X[3], X[1])> + <(X[2],X[0])>
a) Write down the truth tables

Lab Assignment 4
ICS 331 Logic Design & Microprocessors
Fall 2014
Completion Due: 10/2/14
Task 1
a) Get the DLX simulator installed and started on a Lab Computer.
b) Compile the provided program examplecode.s
using the Compiler function of the DLX simulat

HW2 solu)ons
Exercise 1
a) Create all BF(cfw_X1,X2, cfw_XOR) with parse trees that have a height of at most
1 (do not dis)nguish between dierent orders of terms).
0, 1, X1, X2, 0 XOR 0, 0 XOR 1, 0 XOR X1, 0 XO

Homework 2
ICS 331 Digital Logic and Microprocessors
Due: 10/29/14
Exercise 1
Boolean Formulas
a) Create all BF(cfw_X1,X2, cfw_XOR) with parse trees that have a height of at most 1 (do not distinguish
between different orders of terms).
b) How many differ

Homework 4
ICS 331 Digital Logic and Microprocessors
Due: 12/01/14
Tasks
1. An FSD for the control of an ALU is given below. This considers the four states IF, ID, EX
and R-Complete, and the control signals RegWrite, ALUSrcA and ALUOp[1:0]. There are no
i

Homework 3
ICS 331 Digital Logic and Microprocessors
Due: Wed 11/10/14
Exercise 1
Design an Combinational Circuit implementing the Boolean function specified by the following truth
table considering a SOP formula of minterms:
X3
X1
F
0
0
0
0
1
1
1
1
a)
b)

Homework 6
ICS 331 Digital Logic and Microprocessors
Due: 12/11/14
Task
DLX implementation
a) Which control bits have a value of 1 during the 2rd cycle of the instruction and R15, R5, R1?
b) Which control bits do you have to set to 1 to make the datapath

Homework 5
ICS 331 Digital Logic and Microprocessors
Due: 12/11/14
Option 1:
Write a DLX program that implements the game PONG using a 32x32bit Display, a 5-bit position input
device, and a 8 bit hex display.
Assume that the memory addresses from 0x000000

Homework 4
ICS 331 Digital Logic and Microprocessors
Solutions
Tasks
1. An FSD for the control of an ALU is given below. This considers the four states IF, ID, EX
and R-Complete, and the control signals RegWrite, ALUSrcA and ALUOp[1:0]. There are no
input

Homework 6
ICS 331 Digital Logic and Microprocessors
Solutions
Task
DLX implementation
a) Which control bits have a value of 1 during the 2rd cycle of the instruction and R15, R5, R1?
Its the decoding stage where the following bits are set:
Ace, Bce, S2se

Homework 3
ICS 331 Digital Logic and Microprocessors
Solutions
Exercise 1
Design a Combinational Circuit implementing the Boolean function specified by the
following truth table considering a SOP formula of minterms:
X3
X2
X1
F
0
0
0
0
1
1
1
1
0
0
1
1
0
0

Lab Assignment 1
ICS 331 Logic Design & Microprocessors
Fall 2014
Completion Due: 9/9/14
Task 1
a) Install Logisim 2.7.2 on your computer.
b) Work through the Logisim Tutorial Steps 0 to 4 and implemen

Lab Assignment 2
ICS 331 Logic Design & Microprocessors
Fall 2014
Completion Due: 9/16/14
Tasks
a) Implement a function that computes the OR of 32 inputs by using OR gates with two inputs. Test
your circu

Name:
Midterm 2
ICS 331 Digital Logic and Microprocessors
11/25/13
Question 1 Parse trees, Netlists and Combinational Circuits
Consider the following circuit DS:
Right Sft xm X[O]
Y[1] y[0]
based on the choose circuit being defined as OUT = (IN1 AND