Programmable Logic Array (PLA)
The PLA is much more versatile than PROM and PLA, since both its AND-gate
array and its OR-gate array are fusible-linked and programmable.
Assignment: Use PLA to drive Seven Segment Display
GENERATING BOOLEAN FUNCTION:
PROGRAMMABLE ROMS (PROM):
ERASABLE PROGRAMMABLE ROMS (EPROM):
EPROM uses metal-oxide-semiconductor field-effect transistors (MOSFETs).
Data is stored with an EPROM programmer and can be erased
16 X 1 Multiplexer
Figure 1: Logic Diagram
16 X 1 TTL Multiplexer
Pin 1 to 8 and 16 to 23 are for Input Data bits D0
Pin 11, 13, 14 and 15 are the control bits A B C D
Pin 9 is for STROBE, an Input signal that
Parallel Input Serial Output (PISO)
Data bits are entered in parallel fashion.
The circuit shown below is a four bit parallel input serial output register.
Output of previous Flip Flop is connected to the input of the next one via a combinational circuit.
The 74154: 1-to-16 Demultiplexer
Figure 1. Pinout diagram of 74154
Pin 1 to 11 and 13 to 17 are output Bits Y0 to Y15
Pin 18 G1 = DATA ; Pin 19 G2 = STROBE (again Active Low)
Pins 20 t0 23 , A B C D are control bits
Pin 24 = Vcc ; Pin 12 = GND
Figure 2. 7
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T he combinational circuit does not use any memory. Hence the previous state of input does not have any
Logic Design & Switching Theory
Ch. 4: Data Processing Circuits
SEVEN SEGMENT DECODERS
A Seven-Segment Indicator/Display (SSD) is simply a figure eight grouping of LEDs cfw_some include a
decimal point (DP).
Each Segment is labeled (a) thru (g).
Two widely used allocation techniques are contiguous and non-contiguous(Indexing and chaining).
Continuous: In contiguous allocation, files are assigned to contiguous area of secondary storage. The
advantage of this approach is that successive logical