Lecture 7: SPICE
Simulation
Deming Chen
Slides based on the initial set from David Harris
CMOS VLSI Design 4th Ed.
Outline
Introduction to SPICE
DC Analysis
Transient Analysis
Subcircuits
Optimization
Power Measurement
Readings 8.1-8.2
SPICE Simulation
C
Homework 1, due in class on Thursday, Sept. 15, 2016
_
1. Problem 1.6 in textbook. (20 points).
2. Problem 1.18 in text book. (20 points).
3. Sketch gate-level 4:1 multiplexer for the following two cases. Specify whether
your design is restoring or not; a
ECE 425, Fall 2016
Introduction to VLSI System Design
Homework 2 Solution
1. Section 2.5.1 in textbook graphically determined the transfer characteristics of a static
CMOS inverter. Derive analytic expressions for Vout as a function of Vin for regions B
a
ECE 425, Fall 2016
Introduction to VLSI System Design
Homework 2, due in class on Tuesday, Oct. 11, 2016
_
1. Problem 2.16 in textbook. (20 points).
2. Please download SPICE models and characterization scripts from course website.
Use the mosistsmc180 mod
ECE 425/CS 435 Fall 2014
Introduction to VLSI System Design
Homework 2, due in class on Wednesday, Oct. 22, 2014
Sketch an NP Domino 8-input AND circuit. To satisfy the timing requirement, at most 4 transistors are
allowed to be in
1. Sketch an NP Domino 8-input AND circuit. To satisfy the timing requirement, at most 4
transistors are allowed to be in series from output to voltage sours or ground.
Solution:
_
2. The following figure illustrates a 3-bit Manchester Carry Adder. Suppos
ECE 425 Fall 2014
Introduction to VLSI System Design
Homework 3, due in class Monday, Nov. 03, 2014
1. Use the Elmore Delay model to determine the total RC delay from IN1 to OUT.
R5
R3
C4
IN1
IN2
R1
R2
C1
OUT
R4
C3
C1
R6
R7
C5
C6
R8
C7
2. Suppose there is
ECE425 Homework Solutions
Homework 1 Solution
1. A graph G with edges a, b, c, d, e, f, g, h, i, j is given as Figure 1.
a) Please sketch its Dual Graph G0.
b) Please give out the logic functions of G and G0.
c) Suppose the graph G represents an n-network
ECE 425 Fall 2014
Introduction to VLSI System Design
Homework 4, due in class Friday, Dec. 5th, 2014
Min-cut Placement (25 points)
Decide each gates position using recursive min-cut placement method for the
desi
ECE 425 Fall 2014
Introduction to VLSI System Design
Homework 1, due Wednesday in Class, Oct. 1, 2014
1. A graph G with edges a, b, c, d, e, f, g, h, i, j is given as Figure 1.
(a) Please sketch its Dual Graph G0.
(b) Please give out the logic functions o
ECE 425 Fall 2014 HW3 Solutions
Introduction to VLSI System Design
Homework 3, due in class Monday, Nov. 03, 2014
1.
Use the Elmore Delay model to determine the total RC delay from IN1 to OUT.
R5
R3
C4
IN1
IN2
R1
C1
R2
C1
OUT
R4
C3
R6
R7
C5
C6
R8
C7
Solut
ECE 425 Fall 2014
Introduction to VLSI System Design
Homework 4, due in class Friday, Dec. 5th, 2014
1.
Min-cut Placement (25 points)
Decide each gates position using recursive min-cut placement method for the design
shown below
ECE425: Introduction to VLSI System Design
Machine Problem 1
Due:
5:00pm Monday, Sep. 29th 2014
Introduction
This machine problem will introduce cell-based circuit design. You will create a miniature cell library
implementing several basic logic gates. Th
ECE 425: Introduction to VLSI System Design
Machine Problem 0
Due: Friday 5pm, Sep. 5th, 2014
You will spend most of your lab time using the Virtuoso design tools from Cadence Design Systems.
Virtuoso is a set of tools for full-custom silicon chip design,
ECE 425 MP3
Due Monday 5:00pm, December 8th, 2014
In this MP, you will use automated tools to synthesize the controller module from your MP2 project
into a network of standard cells, place those cells onto a layout, and route the cells together into a
com
ECE425 MP2
Fall 2014
Haitong Tian
MP2 Top Level View
output
inv_s
Controller
input
Wire
inv_s
Wire
Wire
inv_s
Datapath
Specify Input & Output & Wire
output
In controller.v
Define the output port inv_s
Assign its value like
inv_s
Controller
input
Wire
i
ECE 425 MP2
CP 1 due on Monday, 5pm, Oct. 27th, 2014
CP 2 due on Monday, 5pm, Nov. 17th, 2014
In this MP and the next, you will create a clone of the AMD Am2901, a datapath chip first introduced
in 1976. We will use a complementary static CMOS design styl
ECE 425 Fall 2016
Introduction to VLSI System Design
Homework 3, due Tuesday, Nov. 29th in class, 2016
_
1. Use synthesizable Verilog to implement the following Mealy machine. (10 points).
S0
S2
S1
Solution:
module fsm (clk, reset, in, out);
input clk, re
ECE 425 Fall 2016
Introduction to VLSI System Design
Homework 3, due Tuesday, Nov. 29th in class, 2016
_
1. Use synthesizable Verilog to implement the following Mealy machine. (10 points).
S0
S2
S1
2. The following combinational logic circuit is implement
ECE425: Introduction to
VLSI System Design
MP2 Overview
Oct 5th, 2016
AMD Am2901
4-bit bitslice datapath unit
Register file
Simple ALU
~500 transistors
Popular in late ~70s
~$5 today
2
Our ASIC Design Flow
MP2
Standard Cell
Library
Synthesis
Full Cu
Lecture 11: Adders
Deming Chen
Slides based on the initial set from David Harris
CMOS VLSI Design 4th Ed.
Outline
Single-bit Addition
Carry-Ripple Adder
Carry-Skip Adder
Carry-Lookahead Adder
Carry-Select Adder
Carry-Increment Adder
Tree Adder
Readings:
Lecture 6: DC & Transient
Response
Deming Chen
Slides based on the initial set from David Harris
CMOS VLSI Design 4th Ed.
Outline
Pass Transistors
DC Response
Logic Levels and Noise Margins
Transient Response
RC Delay Models
Delay Estimation
Readings 2.5
Lecture 4: MIPS
Processor Example
Deming Chen
Slides based on the initial set from David Harris
CMOS VLSI Design 4th Ed.
Outline
Design Partitioning
MIPS Processor Example
Architecture
Microarchitecture
Logic Design
Circuit Design
Physical Design
Lecture 2: IC Fabrication
Deming Chen
Slides based on the initial set from David Harris
Overview
Reading
Textbook: 1.3, 1.5.1-2
Introduction
The essential components of circuits are transistors.
We will introduce the basics of semi-conductor,
transistor
Lecture 12: Datapath
Functional
Units
Deming Chen
Slides based on the initial set from David Harris
CMOS VLSI Design 4th Ed.
Outline
Comparators
Shifters
Multi-input Adders
Multipliers
Readings: 11.3-4; 11.8-9
Datapath Functional Units
CMOS VLSI Design 4
Lecture 14: CAMs, ROMs,
PLAs
Deming Chen
Slides based on the initial set from David Harris
CMOS VLSI Design 4th Ed.
Outline
Content-Addressable Memories
Read-Only Memories
Programmable Logic Arrays
Readings: 12.4-12.7
CAMs, ROMs, and PLAs
CMOS VLSI De
Lecture 8: Logic Effort and
Combinational Circuit
Design
Deming Chen
Slides based on the initial set from David Harris
CMOS VLSI Design 4th Ed.
Outline
Logical Effort
Delay in a Logic Gate
Multistage Logic Networks
Bubble Pushing
Compound Gates
Logical Ef