Post-Lab 10: An Introduction to
High-Speed Addition
Luis Munoz
ECEN 248-507
TA: Yuhan Zhou
Date: April 19, 2015
Objectives:
This lab is designed to teach us why certain circuits are used for certain tasks. For example, we
are going to be looking at carry-
Pre-Lab 10: An Introduction to
High-Speed Addition
Luis Munoz
ECEN 248-507
TA: Yuhan Zhou
Date: April 13,2015
Objectives:
This lab is designed to teach us why certain circuits are used for certain purposes. Also, we are
going to be looking at carry-look a
Post-Lab 11: A Simple Digital
Combination Lock
Luis Munoz
ECEN 248-507
TA: Yuhan Zhou
Date: April 26, 2015
Objectives:
The objective of this lab is to design a circuit that copies the actions of a rotary combination lock
on a circuit board. The standard b
Lab 3: Logic Minimization with Karnaugh Maps
Luis Munoz
ECEN 248 - 507
TA: Yuhan Zhou
Date: February 22, 2015
Objectives:
In this lab I will learn about karnargh maps, minimizing terms, and implementing the minimzed
term into a circuit represented as a pr
Pre-Lab 5: Simple Arithmetic Logic Unit
Luis Munoz
ECEN 248 - 507
TA: Yuhan Zhou
Date: March 2, 2015
Objectives:
In this lab I will learn to design, implement, and test a simple 4-bits Arithmetic Logic Unit. The
use of mux and twos compliment will also be
Lab 5: Simple Arithmetic Logic
Unit
Luis Munoz
ECEN 248-508
TA: Yuhan Zhou
Date: March 08, 2015
Objectives:
This weeks lab involves designing and implementing a 4-bit ALU which can add, subtract, and
AND bits. This lab involves going into Twos Complement
Lab 7: Introduction to
Behavioral Verilog and Logic
Synthesis
Luis Munoz
ECEN 248-511
TA: Yuhan Zhou
Date: March 23, 2015
Objectives:
The objective of this lab is to learn a higher level of Verilog and its uses.
Pre-Lab Deliverables:
1. module t w o f o u
Lab 7: Introduction to
Behavioral Verilog and Logic
Synthesis
Luis Munoz
ECEN 248-507
TA: Yuhan Zhou
Date: March 30,2015
Objectives:
The objective of this lab is to learn a higher level of behavioral Verilog and this is used to
improve the productivity an
Post-Lab 9: Counters, Clock
Dividers, and Debounce
Circuits
Luis Munoz
ECEN 248-507
TA: Yuhan Zhou
Date: April 13,2015
Objectives:
The purpose of this lab is to improve our understanding of sequential circuits and behavioral
Verilog by introducing the bin
Pre-Lab 12: The Traffic Light
Controller Lab
Luis Munoz
ECEN 248-507
TA: Yuhan Zhou
Date: April 26, 2015
Objectives:
The objective of this lab is to be able to incorporate all of the Verilog that we have learned so far
and apply it to a finite state machi
Revised June 30, 2015
Lab 5: Operational Amplifier Application: Electronic Security System
Design: Part 2 of 2
Theory & Introduction
Infrared
Emitter
Current to Voltage Converter Amplifier
Signal
Photo Detector
Comparator
Latch
LEDs
Figure 5.1 Block Diag
Post Lab 5
Luis Munoz, Kaleb Bailey
Lab Done: 10/21/2015
TA: Payman Dehghanian
Summary:
The lab is to demonstrate the combined effect of all pieces performed on lab 4 and with the
addition of LED indicators and an SR latch. Once combined, if obstructed it
Pre-Lab 11: Simple
Combination Lock
Luis Munoz
ECEN 248-507
TA: Yuhan Zhou
Date: April 19, 2015
Objective:
Design a circuit that copies the actions of a combination lock on a circuit board. The circuit will
have to be able to detect and verify the combina
Prelab 3
Luis Munoz
ECEN 214-506
TA: Payman Dehghanian
A. Calculation for Rl
B.
C.
* Creating circuit file "prelab 2-SCHEMATIC1-prelab2_1.sim.cir"
* WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT
SIMULATIONS
*Libraries:
* Loca
Prelab 2
Luis Munoz
ECEN 214-506
TA: Payman Dehghanian
Part A.
a. The value of VL is 0 since its an open
circuit from the switch.
b. The values cannot be determined
without given at least one more piece of
information. Also, the circuit is not
closed.
Par
Assignment 2 ECEN 248 (Spring 2014)
Jan. 24, 2014
Due: Jan 31, 2014 (in class)
Sign the following statement:
On my honor, as an Aggie, I have neither given nor received unauthorized aid on this academic
work
Name:
1.
Using truth tables, prove the validity
ECEN 248: Introduction to Digital System Design
Department of Electrical Engineering
Texas A&M University
Assignment #10
Solutions
1. Suppose I want to build a counter which counts from 0 up to 4 (skipping the value 2). When the
count reaches 4, my counte
ECEN 248: Introduction to Digital System Design
Department of Electrical Engineering
Texas A&M University
Assignment #10
Due Tuesday, December 8, 2009
1. [20 points.] Suppose I want to build a counter which counts from 0 up to 4 (skipping the value 2).
Wh
ECEN 248: Introduction to Digital System Design
Department of Electrical Engineering
Texas A&M University
Assignment #9
Solutions
1. Suppose I have a SOP expression for a funciton f on n-variables, x1 , x2 , xn . Assume that there
are k cubes in the expre
ECEN 248: Introduction to Digital System Design
Department of Electrical Engineering
Texas A&M University
Assignment #9
Due Tuesday, December 1, 2009
1. [15 points.] Suppose I have a SOP expression for a funciton f on n-variables, x1 , x2 , xn . Assume
th
ECEN 248: Introduction to Digital System Design
Department of Electrical Engineering
Texas A&M University
Assignment #8
Solutions
1. Consider a function f = ab + bc.
(a) Write down the recursive Shannon expansion of this function, by using the cofactoring
ECEN 248: Introduction to Digital System Design
Department of Electrical Engineering
Texas A&M University
Assignment #8
Due Thursday,November 19, 2009
1. [20 points.] Consider a function f = ab + bc.
(a) Write down the recursive Shannon expansion of this
ECEN 248: Introduction to Digital System Design
Department of Electrical Engineering
Texas A&M University
Assignment #7
Due Thursday, November 6, 2009
1. [30 points.]
Suppose I want to design a binary multiplier which multiplies an 8 bit number by a 6 bit
ECEN 248: Introduction to Digital System Design
Department of Electrical Engineering
Texas A&M University
Assignment #7
Due Thursday, November 6, 2009
1. [30 points.]
Suppose I want to design a binary multiplier which multiplies an 8 bit number by a 6 bit
ECEN 248: Introduction to Digital System Design
Department of Electrical Engineering
Texas A&M University
Assignment #6
Due Thursday, October 29, 2009
1. [20 points.] Consider the always block below:
always @ (posedge CLK) begin
a = #4 1;
b = #2 1;
a = #2
ECEN 248: Introduction to Digital System Design
Department of Electrical Engineering
Texas A&M University
Assignment #6
Due Thursday, October 29, 2009
1. [20 points.] Consider the always block below:
always @ (posedge CLK) begin
a = #4 1;
b = #2 1;
a = #2
ECEN 248: Introduction to Digital System Design
Department of Electrical Engineering
Texas A&M University
Assignment #5
Due Thursday, October 22, 2009
1. [15 points.]
Consider an output pin of a computer chip A. It is connected to a wire on the printed ci
ECEN 248: Introduction to Digital System Design
Department of Electrical Engineering
Texas A&M University
Assignment #5
Due Thursday, October 22, 2009
1. [15 points.]
Consider an output pin of a computer chip A. It is connected to a wire on the printed ci