EE5323 Homework #5
Dynamic Circuits
Due by 11/26 in class
1. Consider the circuit below.
a. Give the logic function of x and y in terms of A, B, C, and D. Sketch the waveforms at x
and y for the given
EE5323 Homework #4
XOR Gate Schematic and Layout
Reports due by 10/27 in class
In this homework, you are to layout and simulate a two-input exclusive-or (XOR) gate. The
exclusive-or function returns a
EE5323 Homework #1
CMOS Inverter Schematic and Layout
Reports due by 09/29
Please go through the cadence tutorial posted on the class website and get familiar with
the tools before starting the homewo
EE5323 Homework #6
Sequential Logic
YOU DO NOT NEED TO SUBMIT THIS HW
1. For this problem, use the data in the table below.
Register
Latches
Setup time
65ps
25ps
Clk to Q
50ps
50ps
D to Q Contaminatio
ASIC&FPGAChipDesign:
p
g
Verificcation
Dr.Mahd
diShabany
DepartmentofEle
D
t
t f ElectricalEngineering
t i lE i
i
SharifUniversiityoftechnology
CourseC
Code:25266
M.Shabany,ASIC/FFPGAChipDesign
Verifi
Alexandria University
Faculty of Engineering
Electrical Engineering Department
ECE 336: Semiconductor Devices
Sheet 6
Chapter 10:
1. A Si pnp BJT with NAE = 5x1017 / cm3, NDB = 1015/cm3 and NAC = 1014
ECE 3050 Analog Electronics - BJT Formula Summary
Equations are for the npn BJT. For the pnp device, reverse the directions of all current labels and reverse
the order of subscripts involving node lab
Physics 406, Spring 2013
Final Exam
May 10, 2013
Name SQ’KUVEHTMAS
The ten problems are worth 10 points each.
problem Score
1 4 Q
2 4 o
3 4 1 o
4 J 1 O
5 r 40
6 4 O
7 4 O
8 4 0
Alexandria University
Faculty of Engineering
Electrical Engineering Department
ECE 336: Semiconductor Devices
Sheet 6
Chapter 10:
1. A Si pnp BJT with NAE = 5x1017 / cm3, NDB = 1015/cm3 and NAC = 1014
EE5323 Homework #3
Static CMOS Circuits
Due by 10/20/08 in class
1. Consider the circuit below:
a. What is the logic function implemented by the CMOS transistor network? Size the
NMOS and PMOS devices