The majority of the topics covered in this chapter has been related to the steady-state
behavior of the MOS transistor. The current-voltage characteristics investigated here can
be applied for investigating the DC response of MOS circu
Latch up in CMOS.
When CMOS fabrication process follows p-well or n-well process, a problem called
latch up occurs.
Latch up is mainly because of parasitic transistors or large number of junctions
which are formed in these CMOS structures.
Latch up is a c
Layout Design Rules
The physical mask layout of any circuit to be manufactured using a particular process
must conform to a set of geometric constraints or rules, which are generally called layout
design rules. These rules usually specify the minimum allo