CIRCUITS LABORATORY
1
EX.NO.1
VERIFICATION OF KCL AND KVL
VERIFICATION OF KCL
CIRCUIT DIAGRAM:
TO PROVE
I = I 1 + I2
THEORETICAL PROOF:
2
EX.NO.:1
VERIFICATION OF KCL AND KVL
DATE :
AIM:
To verify Kirchoffs Current law and voltage law for the given electr
CS/EE 260 - Exam 1 Solutions
3/5/2001
1. (6 points) Using 40 bits, how many different integers can be represented in (a) binary 2 40 (b) BCD 10 10 (c) 8-bit ASCII? 10 5 2. (12 points) The simulation output on the next page is from an execution of the simp
CS/EE 260 - Exam 2
4/23/2001
1. (10 points) Draw a state diagram for the sequential circuit shown below.
W D Q A >C Q D E Clk Q
Y Z
B
>C Q
-1-
2. (10 points) Answer the following questions, in connection with the circuit in problem 1. Assume that the flip
CS/EE 260 Final Exam
May 4, 2001
You may have one sheet of notes. No calculators. Write in the spaces provided. Be neat.
1. (4 points) Assuming 8 bit words, what is the binary representation of 79?
What is the hexadecimal representation of 79?
What is the
CS/EE 260 - Exam 2 Solutions
4/23/2001
1. (10 points) Draw a state diagram for the sequential circuit shown below.
W D Q A >C Q D E Clk Q
Y Z
B
>C Q
AB 00 01 10 11 00 00 01 01 10 10 11 11
EW D ADB 0x 00 0x 00 0x 00 0x 00 10 01 11 11 10 11 11 01 10 00 11 1
CS/EE 260 Final Exam Solutions
May 4, 2001
You may have one sheet of notes. No calculators. Write in the spaces provided. Be neat.
1. (4 points) Assuming 8 bit words, what is the binary representation of 79? 0100 1111 What is the hexadecimal representatio
Name: ID ti:
Unlverslty of
WEItEfI'IOO
University Of Waterloo
Department of Electrical and Computer Engineering
E&CE 438: Digital integrated Cirouits
Midterm Exam. 8'0?
June 22*". ads? assroom
Time Allowed: 1.5 hours Instruotor: Mohao Anis
Number of Pages
Name: ID #:
University of
Waterloo
<3?
University Of Waterloo
Department of Electrical and Computer Engineering
E&CE 438: Digital integrated Circuits
Midterm Exam. 8'05
June 14th, 2005 5:30-7:00pm
Time Allowed: 1.5 hours Instructor: Mohab Anis
Number of P
Name: ID #:
Problem 1 [12 Marks}:
A CMOS inverter has the voltage transfer characterisitcs show in Figure 1.
o-C 0-0:. u-< an:
9. (a) What are the values of VIL, Vi, VOL, and VOH ?
l
\
l (b) What are these high and low noise margins (NMH and NML)?
1 (c) W
CSE 260 Digital Computers: Organization and Logical Design
Final Exam Solutions
Jon Turner
5/1/2008
1. (8 points) Consider the two timing diagrams shown below. One shows the output of a CMOS NAND gate in response to a change on one of its inputs. The othe
CS/EE 260 - Exam 1
3/5/2001
1. (6 points) Using 40 bits, how many different integers can be represented in (a) binary,
(b) BCD,
(c) 8-bit ASCII?
-1-
2. (12 points) The simulation output on the next page is from an execution of the simple processor introdu