EEC 170: Homework 6 Solution
Problem 1 (Pipeline Design)
We want to add the instruction Store Word Indexed (SWI) to the MIPS architecture. SWI Rt,Rd(Rs) performs the
operation: Mem[Reg[Rd]+Reg[Rs]=Reg[Rt]. Illustrate on Figure 4.65 the modifications that
EEC 170: Homework 7 Solution
Problem 1 (Virtual Memory)
From our text, exercises 5.10.1 and 5.10.2 using the stream of virtual addresses:
4095, 31272, 15789, 15000, 7193, 4096, 8912
5.10.1
Virtual page number 20 MSBs
H: Hit in TLB, M: Miss in TLB hit in p
EEC 170: Homework 5 Solution
Problem 1 (Pipeline Speedup)
Given these functional units, how much faster is a pipelined processor than the single
cycle implementation assuming no data hazards and no branch hazards.
Non-pipelined
200ps + 100ps + 150ps + 200
EEC 170: Homework 4 Solution
Problem 1 (Wallace Tree Multiplier)
Determine the number of stages needed for the complete column height reduction and
determine the height of each bit position in each of the following stages.
The entries in blue are where ha
EEC 170: Homework 3 Solution
P ro b l e m 1
For the constant 0xAD100002, show the minimum length MIPS code sequence and the
minimum length ARM code sequence that stores this constant in register 1.
MIPS
lui $1, 0xAD10 # $1 = 0xAD10 < 16
ori $1, 0x0002 # $
EEC 170: Homework 2 Solution
P ro b l e m 1
Part A
i) f = g - A[B[17]
lw
s ll
ad d
lw
su b
$t0, 68($t4)
$t0, $t0, 2
$t0, $t0, $t3
$t0, 0($t0)
$t0, $t1, $t0
# Loading B[17]
# 4*B[17]
# BaseAddr(A) + 4*B[17]
# Loading A[B[17]
# g - A[B[17]
ii) f = A[B[g]+1
EEC 170: Homework 1 Solution
P ro b l e m 1
1.4.4
Arithmetic cc = 500cc
Load/Store cc = (100+50) * 5 = 750cc
Branch cc = 50*2 = 100cc
Total Clock Cycles = 500 + 750 + 100 = 1350cc
Exec. Time = (total cc)/clock rate =
1.4.5
1.4.6
New Execution Time: 500cc
EEC 170 Homework Assignment 7
Virtual Memory
Deposit in EEC170 HW Box in 2131 Kemper
Due Friday, Dec. 2 11:55PM
Problem 1, Virtual Memory: from our text, exercises 5.10.1 and 5.10.2 using the stream of virtual addresses:
4095, 31272, 15789, 15000,7193, 40
EEC 170 Homework Assignment 6
Pipelining/Cache
Deposit in EEC170 HW Box in 2131 Kemper
Due Thursday, Nov. 17 11:00PM
Problem 1: Pipeline Design: We want to add the instruction Store Word Indexed (SWI) to the MIPS
architecture. SWI Rt,Rd(Rs) performs the o
EEC 170 Homework Assignment 5
Pipelining
Deposit in EEC170 HW Box in 2131 Kemper
Due Thursday, November 10, 11:00PM
Problem 1 (Pipeline Speedup):
Assume the following delays for each processor functional unit:
Inst Fetch Reg Read ALU Data Mem Reg Write Pi
EEC 170 Homework Assignment #4
Arithmetic
Deposit in EEC170 HW Box in 2131 Kemper
Due Thursday, October 27, 11:00PM
Problem 1 (Wallace Tree Multiplier):
Shown in the table below is the initial colum height (L = 0) for a 16x16 bit Wallace Tree multiplier,
EEC 170 Homework Assignment #3 Fall 2011
Instruction Sets
Deposit in EEC170 HW Box in 2131 Kemper
Due Thursday, October 20, 11:00PM
Problem 1: For the constant 0xAD100002, show the minimum length MIPS code
sequence and the minimum length ARM code sequence
EEC 170 Homework Assignment #2 Fall 2011
Instruction Sets
Deposit in EEC170 HW Box in 2131 Kemper
Due Thursday, October 13, 11:00PM
Problem 1 (Addressing Modes):
(a) Translate the following to C statements into a minimum number of MIPS instructions.
Assum
EEC 170 Fall 2011 Homework Assignment #1
Deposit in EEC170 HW Box in 2131 Kemper
Due Thursday, October 6, 11:00PM
Problem 1 (Computer Performance): From our text, Exercise 1.4, sub-problems 1.4.4
through 1.4.6.
Problem 2 (Power wall): From our text, Exerc