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EE/CSl68 Introduction to VLSI Design W16 3. §
Instructor: Sheldon Tan ‘
Midterm Two 3 . 6
Name: WWW“; EM
Date: 9% '7 [ibié
Please use the 180 nm process parameters shown at the end of midterm for the questions. For
NMOS as Rn = 6.47KQ,
EE/CSI68 Introduction to VLSI Design W16
Instructor: Sheldon Tan
Midterm
Name: “(ileum KM
Date: '23} [2M6 _
Please use the 180 nm process parameters shown at the end of midterm for the questions. For
NMOS as Rn = 6.47KQ, for PMOS as RD = 29.6KQ, Cl =0.89f
EECS 168
Introduction to VLSI Design
Sheldon Tan
Homework 1 answers
1. (10 pts). Assuming Vgs is 3V, compute the drain current through a ntype transistor at
a Vds of 1.8V, where W/L is 6/2, k=73A/V2, and Vt is 0.7V.
Vgs Vt = 3V 0.7V = 2.3V
Vds < Vgs Vt

EECS 168
Introduction to VLSI Design
Sheldon Tan
Homework 4
1. (30pts) (a) Draw the schematic of the logic circuit described by the Verilog code
below:
module pie( x, y, a, b, c);
input a, b, c;
wire t1, t2;
output x,y;
xor #2 x1(t1,a,b);
not #1 n1(x,t1);
EECS 168
Introduction to VLSI Design
Sheldon Tan
Homework 3
Please use the 180 nm process parameters shown at the end of homework for all the
homework questions. For NMOS as Rn = 6.47K, for PMOS as Rp = 29.6K, and Cl
=0.89f F)
1. (10pt) Draw the transisto
EECS 168
Introduction to VLSI Design
Sheldon Tan
Homework 1 answers
1. (10 pts). Assuming an ntype transistor with Vds of 1.8V and Vt of 0.7V, find the
ranges of Vgs to put the transistor in cutoff, linear, and saturation regions.
Cutoff: Vgs < Vt
so Vgs
EECS 168
Introduction to VLSI Design
Sheldon Tan
Homework 2
Please use the 180 nm process parameters shown at the end of homework for all the
homework questions. For NMOS as Rn = 6.47K, for PMOS as Rp = 29.6K, and Cl
=0.89f F)
1. Design the static complem
EECS 168
Introduction to VLSI Design
Sheldon Tan
Homework 1
1. (10 pts). Assuming an ntype transistor with Vds of 1.8V and Vt of 0.7V, find the
ranges of Vgs to put the transistor in cutoff, linear, and saturation regions.
2. (10 pt). Assume a NMOS has V