[4/7ng O (y 37
4‘.
EE/CSl68 Introduction to VLSI Design W16 3. §
Instructor: Sheldon Tan ‘
Midterm Two 3 . 6
Name: WWW“; EM
Date: 9% '7 [ibié
Please use the 180 nm process parameters shown at the end
EE/CSI68 Introduction to VLSI Design W16
Instructor: Sheldon Tan
Midterm
Name: “(ileum KM
Date: '23} [2M6 _
Please use the 180 nm process parameters shown at the end of midterm for the questions. For
EECS 168
Introduction to VLSI Design
Sheldon Tan
Homework 1 answers
1. (10 pts). Assuming Vgs is 3V, compute the drain current through a n-type transistor at
a Vds of 1.8V, where W/L is 6/2, k=73A/V2,
EECS 168
Introduction to VLSI Design
Sheldon Tan
Homework 4
1. (30pts) (a) Draw the schematic of the logic circuit described by the Verilog code
below:
module pie( x, y, a, b, c);
input a, b, c;
wire
EECS 168
Introduction to VLSI Design
Sheldon Tan
Homework 3
Please use the 180 nm process parameters shown at the end of homework for all the
homework questions. For NMOS as Rn = 6.47K, for PMOS as Rp
1.
2.
3.
4.
5.
HW1
SinceV
=1.8V<V t
V
=(30.7)=2.3V,therefore,thelinearregionoccurs.
ds
gs
6
2
4
I
=73*10
*3[(30.7)1.81.8
*0.5]=5.52*10
A
d
Wesetthelinearandsaturationequationsequaltoeachotherbecausew
EECS 168
Introduction to VLSI Design
Sheldon Tan
Homework 1 answers
1. (10 pts). Assuming an n-type transistor with Vds of 1.8V and Vt of 0.7V, find the
ranges of Vgs to put the transistor in cutoff,
EECS 168
Introduction to VLSI Design
Sheldon Tan
Homework 2
Please use the 180 nm process parameters shown at the end of homework for all the
homework questions. For NMOS as Rn = 6.47K, for PMOS as Rp
EECS 168
Introduction to VLSI Design
Sheldon Tan
Homework 1
1. (10 pts). Assuming an n-type transistor with Vds of 1.8V and Vt of 0.7V, find the
ranges of Vgs to put the transistor in cutoff, linear,