[CSM51A W09] Assignment 6
Assigned: 02/16/09, Due: 02/23/09 TAs: Pouya Dormiani ([email protected]), Gabriel Pan ([email protected])
Rules of Engagement: Exercises are for your practicesolutions are provided so you can check your work. Homework problems m
[CSM51A W09] Solution to Assignment 6
Assigned: 02/16/09, Due: 02/23/09 TAs: Pouya Dormiani ([email protected]), Gabriel Pan ([email protected])
Homework Problems (45 points total)
Problem 1 (15 points)
Our goal is to design a vending machine which sells
318
Chapter 9
Standard combinational modules
In this chapter, we present A set of widely used standard combinational modules. The speci cation of these standard modules. A gate network implementation for each of these standard modules. The main uses of th
16
Chapter 2
Speci cation of combinational systems
In this chapter, we present and discuss The high-level and binary-level speci cations. The representation of data elements (signal values) by binary variables (signals) and the standard codes for positive
119
Chapter 8
problem. (a) The minimum delay of the combinational network (tp ) considered in this problem is obtained by the following equation tp + 2ns 5ns ! tp 3ns (b) If the delay of the combinational network can decrease by 30% and the latch delay ca
Solutions Manual - Introduction to Digital Design - October 3, 2000
Exercise 5.4
(a) Kmap and prime implicants
f (w; x; y; z) = P m(0; 1; 2; 3; 5; 7; 8; 10; 11; 15)
z 1 0 0 1
0 0
59
w
1 1 0 0
1 1 1 1 y
1 0 0 1
x
prime implicants: w x ; w z; x y; yz; x z (
[CSM51A W09] Assignment 7
Assigned: 02/23/09, Due: 03/02/09 TAs: Pouya Dormiani ([email protected]), Gabriel Pan ([email protected])
Rules of Engagement: Exercises are for your practicesolutions are provided so you can check your work. Homework problems m
[CSM51A W09] Assignment 4
Assigned: 02/02/09, Due: 02/09/09 TAs: Pouya Dormiani ([email protected]), Gabriel Pan ([email protected])
Rules of Engagement: Exercises are for your practicesolutions are provided so you can check your work. Homework problems m
[CSM51A W09] Assignment 2
Assigned: 01/19/09, Due: 01/26/09 TAs: Pouya Dormiani ([email protected]), Gabriel Pan ([email protected])
Rules of Engagement: Exercises are for your practicesolutions are provided so you can check your work. Homework problems m
[CSM51A W09] Assignment 1
Assigned: 01/12/09, Due: 01/19/09 TAs: Pouya Dormiani ([email protected]), Gabriel Pan ([email protected])
Rules of Engagement: Exercises are for your practicesolutions are provided so you can check your work. Homework problems m
450
Chapter 12
Programmable modules
In this chapter we present: The speci cation of programmable combinational and sequential modules (psa, rom, pga). The way the modules are programmed. Examples of uses of these modules. The last chapters have discussed
Chapter 11
Standard sequential modules
In this chapter, we present A set of widely used standard sequential modules. The speci cation of these standard modules. An implementation with ip- ops and gates for each of these standard modules. The main uses of
Chapter 10
Arithmetic combinational modules and networks
In this chapter we describe: The speci cation of adder modules for positive integers. Half-adder and full-adder modules. Carry-ripple and carry-lookahead adder modules. Networks of adder modules. Th
STANDARD COMBINATIONAL MODULES
1
DECODERS ENCODERS MULTIPLEXERS (Selectors) DEMULTIPLEXERS (Distributors) SHIFTERS
Introduction to Digital Systems
9 Standard Combinational Modules
BINARY DECODERS
2
HIGH-LEVEL DESCRIPTION: Inputs: x = (xn1, . . . , x0), x
Chapter 8
Sequential networks
In this chapter we discuss: Canonical form of sequential networks: state register plus combinational network. Characteristics of binary cells: latches and edge-triggered cells. The D ip- op. Timing parameters for cells and ne
214
Chapter 7
Speci cation of sequential systems
The main topics of this chapter are The de nition of synchronous sequential systems. The state description and time behavior of sequential systems. Mealy and Moore machines. Finite-memory systems. The descr
SPECIFICATION OF SEQUENTIAL SYSTEMS
1
SYNCHRONOUS SEQUENTIAL SYSTEMS MEALY AND MOORE MACHINES TIME BEHAVIOR STATE MINIMIZATION
Introduction to Digital Systems
7 Specication of Sequential Systems
DEFINITION
2
z (t) = F (x(0, t)
x
x(t)
z z(t) time t
Figure
Chapter 5
Design of combinational systems: two-level gate networks
In this chapter we present Design of two-level gate networks: and-or and or-and networks. Minimal two-level networks. Karnaugh maps. Minimization procedure and tools. Limitations of two-le
Chapter 4
Description and analysis of gate networks
In this chapter, we discuss The de nition, description, and characteristics of gate networks. Alternative sets of gates that compose networks. The analysis of gate networks: determination of the function
76
Chapter 3
Combinational integrated circuits: characteristics and capabilities
In this chapter, we discuss The representation of binary variables at the physical level. The basic switch structure of gates and their operation. The realization of gates us
COMBINATIONAL ICs
REPRESENTATION OF BINARY VARIABLES AT THE PHYSICAL LEVEL BASIC SWITCH. STRUCTURE OF GATES AND THEIR OPERATION REALIZATION OF GATES USING cmos CIRCUITS
1
CHARACTERISTICS OF CIRCUITS: LOAD FACTORS AND FANOUT FACTORS, PROPAGATION DELAYS,
SPECIFICATION OF COMBINATIONAL SYSTEMS
HIGH-LEVEL AND BINARY-LEVEL SPECIFICATIONS
1
REPRESENTATION OF DATA ELEMENTS BY BINARY VARIABLES; STANDARD CODES FOR POSITIVE INTEGERS AND CHARACTERS REPRESENTATION BY SWITCHING FUNCTIONS AND SWITCHING EXPRESSIONS
Chapter 1
Introduction
In this chapter, we discuss What is a digital system and how it di ers from an analog system. Why are digital systems important and where are they used. The basic types of digital systems: combinational and sequential. The speci cat
642
Appendix A
Boolean algebras
used in the description of switching expressions discussed in Section 2.4, is an instance (an element) of the class of Boolean algebras. Consequently, theorems developed for Boolean algebras are also applicable to switching
119
Chapter 8
problem. a The minimum delay of the combinational network tp considered in this problem is obtained by the following equation tp + 2ns 5ns ! tp 3ns b If the delay of the combinational network can decrease by 30 and the latch delay can decrea
99
Chapter 7
Exercise 7.1
Input:
Output: Function:
xt 2 fa; b; cg z t 2 fp; qg
z t = q if number of a's in x0; t , 1 is even and number of b's is odd. p otherwise
State:
st = sa t; sb t sat = number of a's mod 2 sb t = number of b's mod 2
Initial state:
s
85
Chapter 6
Exercise 6.1 From Exercise 5.11, we know that the single-error detector for a 2-out-of-5 code a; b; c; d; e is implemented by the expression: E a; b; c; d; e = abc + abd + acd + bcd + abe + ace + ade + bce + bde + cde + a b c e + a b d e + ac
55
Chapter 5
Exercise 5.1
z x 0101 0100 y x
z -011 -001 y
f1
Exercise 5.2
f0
a the K-map for E x; y; z =
P m1; 5; 7 is:
z x 0100 0110 y
0
bE w; x; y; z = w x y + y z + xz
0 0 0
z 0 1 1 0 1 1 1 1 1 0 0 0 y
Exercise 5.3
w
1 1 1 0
x
a E w; x; y; z = M 1; 3;
41
Chapter 4
Exercise 4.1
a gure 4.17a presents a valid gate network b the network in gure 4.17b is not valid since: the load factor L imposed to one of the 2-input AND gates exceeds the fan-out factor F of this gate; two outputs are connected together. c
37
Chapter 3
Exercise 3.1
December 10, 1998
a logic values Voltage V Positive Logic Negative Logic 1.0 0 1 4.5 1 0 2.0 unde ned unde ned -1.0 unde ned unde ned
b module has the following behavior voltage levels: Positive Logic Negative Logic 0.3 0.3 4.5 4