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Score
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CS M51A and EE M16 Winter 2006 Section 1
Logic Design of Digital Systems
Dr. Yutao He
Homework Assignment No. 4
Due: February 6, 2006
Textbook: Chapters 5 and 6
Problems:
Ch.5: 5.6 (a,b), 5.7, 5.8, 5.15, 5.19
Ch.6: 6.4, 6.8
Notes:
Name
Score
Last
First
CS M51A and EE M16 Winter 2005 Section 1
Logic Design of Digital Systems
Dr. Yutao He
Homework Assignment No. 3
Due: January 31, 2005
Textbook: Chapters 3 and 5
Problems:
Ch.3: 3.1, 3.6, 3.7
Ch.5: 5.1, 5.2(b), 5.4, 5.6(a,b), 5.7, 5
R
A
B
S
T
X
Y
C
E
D
Z
x1
T2
z1
x0
T1
T3
z0
T4
x1
T2
z1
x0
T1
T3
z0
T4
C
A
0
0
B
M0
y
A
0
1
B
M0
A
1
2
B
M0
A
2
B
3
M0
3
z
x
x0
x1
x2
M1
c1
c0
M2
0
M3
c2
M5
S
x3
M5
S
1
M4
c3
M5
S
2
M5
S
3
C
4
Problem 2
Given the radix 2 digit vector: X = 11100
Calculate t
INTRODUCTION TO DIGITAL SYSTEMS DESCRIPTION AND DESIGN OF DIGITAL SYSTEMS FORMAL BASIS: SWITCHING ALGEBRA IMPLEMENTATION: MODULES (ICs) AND NETWORKS IMPLEMENTATION OF ALGORITHMS IN HARDWARE COURSE EMPHASIS: CONCEPTS, ANALYSIS AND DESIGN Follow-on courses:
Name
Score
Last
First
CS M51A and EE M16 Winter 2006 Section 1
Logic Design of Digital Systems
Dr. Yutao He
Homework Assignment No. 3
Due: January 30, 2006
Textbook: Chapters 3 and 5
Problems:
Ch.3: 3.1, 3.6, 3.7
Ch.5: 5.1, 5.2(b), 5.4, 5.6(a,b), 5.7, 5
CS M51A and EE M16 Logic Design of Digital Systems
Winter 2006
Homework #4 Solution
Yutao He
February 9, 2006
Problem 5.6 (minimal product of sums only)
(a) E (w, x, y, z ) = M (1, 3, 4, 7, 10, 13, 14, 15) =
z
w
m(0, 2, 5, 6, 8, 9, 11, 12)
1 0
0
1
01
0
Name
Score
Last
First
CS M51A and EE M16 Winter 2005 Section 1
Logic Design of Digital Systems
Dr. Yutao He
Homework Assignment No. 4
Due: February 7, 2005
Textbook: Chapters 5 and 6
Problems:
Ch.5: 5.6 (a,b), 5.7, 5.8, 5.15, 5.19
Ch.6: 6.4, 6.8
Notes:
CS M51A and EE M16 Winter 2005 Section 1
Logic Design of Digital Systems
Dr. Yutao He
VHDL Lab #3 - Design of Sequential Systems
Due: March 11, 2005
(1) Name:
Last
First
Last
First
Student ID:
(2) Name:
Student ID:
Date:
Result
Correctness
Creativity
Repo
Name:
SID:
Last
First
UCLA COMPUTER SCIENCE DEPARTMENT
Quiz 4 - Rehearsal
CS M51A and EE M16 Winter 2006 Section 1
Logic Design of Digital Systems
March 15, 2006
Dr. Yutao He
Rule:
This is an open-book and rehearsal quiz. It is intended to give you a snea
CS M51A/EE M16 Winter05 Section 1
Logic Design of Digital Systems
Lecture 1
January 10
W 0
Outline
Welcome
Chapter 1 - Class Overview
Summary
5
Yutao He
[email protected]
4532B Boelter Hall
http:/courseweb.seas.ucla.edu/classView.php?term=05W&srs=18715
CS M51A/EE M16 Winter05 Section 1
Logic Design of Digital Systems
Lecture 11
February 23
W 0
Outline
Administrative Matters
Chapter 7
Specification of Sequential Systems
State Minimization
5
Yutao He
yutao@ cs.ucla.edu
4532B Boelter Hall
http:/ course
CS M51A/EE M16 Winter05 Section 1
Logic Design of Digital Systems
Lecture 10a
February 16
W 0
Outline
Administrative Matters
Arithmetic modules Wrap-up
Midterm Sneak Preview
Q & A Sessions
5
Yutao He
yutao@ cs.ucla.edu
4532B Boelter Hall
http:/courseweb.s
CS M51A and EE M16 Winter 2005 Section 1
Logic Design of Digital Systems
Dr. Yutao He
VHDL Lab #1 - Orientation of MAX+plus II and VHDL
Due: February 23, 2005
Name:
Last
First
Student ID:
Date:
Result
Correctness
Creativity
Report
Total Score
1
VHDL Lab #
CS M51A/EE M16 Winter05 Section 1
Logic Design of Digital Systems
Lecture 17 - Grande Finale
March 16
W 0
Outline
Breaking News
Chapter 12
Read-Only Memory (ROM)
The Class Review
The Final Review and Sneak Preview
Course evaluation
5
Yutao He
yutao@
CS M51A/EE M16 Summer15 Section 1
Logic Design of Digital Systems
Lecture 13
August 6, 2015
Yutao He
[email protected]
4532B Boelter Halll
http:/ccle.ucla.edu/course/view/151A-COMSCIM51A-1
CSM51A/EEM16-Sec.1 Su 15
L13.1
Y. He @ 8/6/15
Outline
Chapter 8 W
CS M51A/EE M16 Winter05 Section 1
Logic Design of Digital Systems
Lecture 8
February 7
W 0
5
Outline
Administrative Matter
Review: Design of combinational systems
Chapter 4: Analysis of combinational systems
Summary
Yutao He
yutao@ cs.ucla.edu
4532B Boelt
CS M51A/EE M16 Winter05 Section 1
Logic Design of Digital Systems
Lecture 6
January 31
Outline
Administrative Matters
Recap
Minimization with K-Map using implicants and friends
Chapter 5
W 0
Minimization with K-Map using implicates and friends
Minim
CS M51A and EE M16 Winter 2005 Section 1
Logic Design of Digital Systems
Dr. Yutao He
VHDL Lab #2 - Design of Combinational Systems
Due: March 2, 2005
(1) Name:
Last
First
Last
First
Student ID:
(2) Name:
Student ID:
Date:
Result
Correctness
Creativity
Re
Name:
SID:
Last
First
CS M51A and EE M16 Winter 2005 Section 1
Logic Design of Digital Systems
Dr. Yutao He
Quiz #1
January 21, 2005
This is a closed-book, closed-note, and independent quiz (30 minutes). No calculator or
scratch paper is allowed. Write do
CS M51A/EE M16 Summer15 Section 1
Logic Design of Digital Systems
Lecture 9
July 23, 2015
Yutao He
[email protected]
4532B Boelter Halll
http:/ccle.ucla.edu/course/view/151A-COMSCIM51A-1
CSM51A/EEM16-Sec.1 Su 15
L9.1
Y. He @ 7/23/15
Outline
Administrativ
CS M51A/EE M16 Summer15 Section 1
Logic Design of Digital Systems
Lecture 8
July 16, 2015
Yutao He
[email protected]
4532B Boelter Halll
http:/ccle.ucla.edu/course/view/151A-COMSCIM51A-1
CSM51A/EEM16-Sec.1 Su 15
L8.1
Y. He @ 7/16/15
Outline
Lecture #7 Re
CSM51A Discussion #6
Hyunjin Kim
Outline
Review HW5
Chapter 8
Timing Parameters of Flipflops
Chapter 7
Mealy vs. Moore machine
State transition table
State Diagram
State Minimization
Violation of set-up time or hold time causes a undefined output.
CS M51A/EE M16 Winter05 Section 1
Logic Design of Digital Systems
Lecture 13
March 2
W 0
Outline
Administrative Matters
Basic sequential devices - Recap
Design of sequential systems w/ FFs
Analysis of sequential systems
Timing Analysis
Functional analys