CS M51A / EE M16
Winter 2016
Homework #5
Problem 1: Implement the following program repeatedly using a single 8-bit
adder/subtracter (AS) module, 8-bit registers, as few as possible as small as possib
UCLA
Department of Electrical Engineering
EEM16 Fall 2011
Discussion 9
1. Ex. 10.5
Design a one-digit decimal adder in the Excess-3 code. Use two four-bit binary
adders and one inverter.
2. Complete t
Chapter 1: Introduction to Digital Systems
1.1DIGITAL SIGNALS
Digital systems store, process, and transport information in digital form
We represent information with 0,1 and encode this symbols into
Chapter 6: Combinational Logic Design
6.1 COMBINATIONAL LOGIC
Combinational logic circuits implement logical functions on a set of inputs for
control, arithmetic, and data steering.
A combinational
Chapter 8: Combinational Building Blocks
8.1 MULTI-BIT NOTATION
We use bus notation to denote multi-bit signals with a single line and a slash
across it.
8.2 DECODERS
A decoder convers a binary to a
Chapter 1: Introduction to Digital Systems
1.1DIGITAL SIGNALS
Digital systems store, process, and transport information in digital form
We represent information with 0,1 and encode this symbols into
Chapter 10: Arithmetic Circuits
10.1 BINARY NUMBERS
In digital electronics we have two states, 1 and 0, with which to represent
with values
For a binary number x we have the value v:
n1
v = x i 2i
i
EEM16 Discussion 7
Jun Wang
11/9/2012
Skip this for now
Review Canonical Implementation of Sequential Networks
Review Timing Characteristics of Sequential Networks
Goal: build system with combinationa
UCLA
Department of Electrical Engineering
EEM16 Fall 2011
Discussion3
1. Ex. 2.41
Determine the sum of minterms and product of maxterms that are equivalent to
E ( x , y , z )=x ' + x ( x ' y + y ' z )
UCLA
Department of Electrical Engineering
EEM16 Fall 2011
Discussion 7
1. Ex. 7.22
A sequential system has a decimal digit as input and a radix-5 digit as output. The
output counts modulo-5 the number
UCLA
Department of Electrical Engineering
EEM16 Fall 2011
Discussion 10
1. Ex. 10.19
Design an iterative binary comparator in which the internal variable (carry) goes in
the direction from most-signif
Name
First
Last
Student ID #
Random #
University of California
Los Angeles
Computer Science Department
CSM51A Sec 2 Final Exam
Winter Quarter 2009
March 19, 2009
This is a closed book exam. Absolutely
Name
First
Last
Student ID #
University of California
Los Angeles
Computer Science Department
CSM51A/EEM16 Final Exam
Fall Quarter 2012
Dec. 12th 2012
This is a closed book exam. Absolutely nothing is
UCLA
Department of Electrical Engineering
EEM16 Fall 2011
Discussion2 Solution
1. Ex 2.3
2. Ex 2.11
3. Combinational Logic Design: Write the (i) high-level description, (ii) truth
table, and (iii) one
UCLA
Department of Electrical Engineering
EEM16 Fall 2011
Discussion2
1. Ex 2.3
Give a high-level specification of a combinational system that computes the
distance between two 1s in the input bit-vec
UCLA
Department of Electrical Engineering
EEM16 Fall 2011
Discussion4 Solution
1. Ex. 4.7
2. The longest path is:
X 1 A2 O2 X 2
(choose
X1
not
A1
because XOR gates have longer delay than AND gates)
T
UCLA
Department of Electrical Engineering
EEM16 Fall 2011
Discussion4
1. Ex. 4.7
Show that the operation (gate) represented by the switching expression
'
'
x yz +x y + y ' z
is universal. You can use
UCLA
Department of Electrical Engineering
EEM16 Spring 2009
Midterm
April 3011,2009 SO LUTl 0N8
_._._
M
. Exam IS closed book. You are allowed one 8 1/z x 11 double-sided cheat sheet.
. Calculators ar
UCLA
Department of Electrical Engineering
EEM16 Fall 2011
Discussion 8
1. Ex. 8.4 (timing analysis only)
For the canonical sequential network shown in Figure 8.40, determine the timing
factors (in ter
EEM16 Discussion 8
Jun Wang
11/16/2012
One flip-flop per state or one-hot approach is a brute force approach.
Example: Take a three state system. Use three binary digits to represent. Each binary
digi
EEM16 Discussion 10
Jun Wang
12/7/2012
Part a (1 bit per cycle)
S1: After the clear signal the counter is in state 0 and the NOR gate forces a 1 input
into the half adder
S2: The other input of the
Discussion Note EEM16 Week4 1. Time behavior -> state description -> state diagram Ex. 7.11 Describe the time behavior of a modulo-p counter assuming that any of the p states can b
Discussion Note EEM16 Week2 1. Canonical forms - Ex 2.41 Determine the sum of minterms and product of maxterms that are equivalent to E(x,y,z) = x + x (xy+yz) 2. Generalized DeMorgans theorem (A+B+C+D
Discussion Note EEM16 Week1 1. Digital signal v.s. analog signal 2. Number system (i) (47)10 = (?)2 (ii) Ex. 2.13 (a) Determine the radix-16 representation of the integer whose radix-2 representation
DESIGN OF MULTILEVEL NETWORKS
1
TRANSFORMATIONS TO SATISFY CONSTRAINTS - number of gate inputs - network size - network delay DESIGN OF NETWORKS WITH xor and xnor GATES DESIGN OF NETWORKS WITH multip
DESIGN OF GATE NETWORKS
1
DESIGN OF TWO-LEVEL NETWORKS: and-or and or-and NETWORKS MINIMAL TWO-LEVEL NETWORKS KARNAUGH MAPS MINIMIZATION PROCEDURE AND TOOLS LIMITATIONS OF TWO-LEVEL NETWORKS DESIGN O
COMBINATIONAL ICs
REPRESENTATION OF BINARY VARIABLES AT THE PHYSICAL LEVEL BASIC SWITCH. STRUCTURE OF GATES AND THEIR OPERATION REALIZATION OF GATES USING cmos CIRCUITS
1
CHARACTERISTICS OF CIRCUITS
UCLA
Department of Electrical Engineering
EEM16 Fall 2012
Homework 3
Due Oct 25, 2012
(This homework contains 5 problems)
Problem 1 Ex 4.7
Show that the operation (gate) represented by the switching e
UCLA
Department of Electrical Engineering
EEM16 Fall 2013
Discussion 5
1. Ex. 6.11
Show a tree of multiplexers implementing the expressions:
a.
E ( a , b , c , d )=a' b +a' b' c' +b c ' d+ ab d ' + b
UCLADepartment of Electrical Engineering
EEM16 Fall 2012
Discussion 3 Solutions
Problem 1: Exer. 2.43
Convert the following SEs into product of maxterms without obtaining the sum of
minterms first
' '
EEM16 Discussion 9
Jun Wang
11/30/2012
Basically
e.g. if then
The sum in E3 code
Function of the desired module
Function of the given module
Use as indicator for two conditions of the desired module
=
UCLA
Department of Electrical Engineering
EEM16 Fall 2012
Discussion 7
1. Ex 7.21
A sequential system has an input set I =cfw_a , b , c , d and an output set O=cfw_0,1 .
The output is 1 when the patt