[CS M51A Winter 12] Assignment 4
Assigned: 02/18/12, Due: 02/24/12
TAs: Neil Conos ([email protected]), Gabriel Pan ([email protected])
Rules of Engagement: Homework problems must be submitted on the specied due date before discussion starts. Once discuss
CS M51A / EE M16
Winter 2011
Homework #5
Problem 1: Implement the following program repeatedly using a single 8-bit
adder/subtracter (AS) module, 8-bit registers, as few as possible as small as possible
counters and combinational modules of your choice.
T
-So\ut;an
NAME
First
Last
Student ID#
UNIVERSITY OF CALIFORNIA
LOS ANGELES
COMPUTER SCIENCE DEPARTMENT
MIDTERM EXAMINATION #l
CSM51A/EEM16
Fall Quarter 2005
November 2, 2005
This is a closed-book exam. (100 minutes)
Use this form for your work and return
[CS M51A Winter 10] Assignment 6
Assigned: 03/09/12, Due: 03/16/12
TAs: Neil Conos ([email protected]), Gabriel Pan ([email protected])
Rules of Engagement: Homework problems must be submitted on the specied due date before discussion starts. Once discuss
UNIVERSITY OF CALIFORNIA
LOS ANGELES
COMPUTER SCIENCE DEPARTMENT
MIDTERM EXAMINATION - SOLUTIONS
CS M51A
Fall Quarter 2002
October 24, 2002
MIDTERM SOLUTIONS
1
CSM51A/EEM16
October 24, 2002
Find x, y, and z such that the following conditions are satised:
[CS M51A Winter 12] Solution to Assignment 5
Assigned: 03/02/12, Due: 03/09/12
TAs: Neil Conos ([email protected]), Gabriel Pan ([email protected])
Homework Problems (50 points total)
Problem 1 (10 points)
We would like to analyze the timing required for
[CS M51A Winter 12] Solution to Assignment 3
Assigned: 02/03/12, Due: 02/10/12
TAs: Neil Conos ([email protected]), Gabriel Pan ([email protected])
Homework Problems (70 points total)
Problem 1 (20 points)
For f (x, y, z, w) =
M (1, 8, 9, 12)
1. Using K-m
[CS M51A Winter 12] Assignment 5
Assigned: 03/02/12, Due: 03/09/12
TAs: Neil Conos ([email protected]), Gabriel Pan ([email protected])
Rules of Engagement: Homework problems must be submitted on the specied due date before discussion starts. Once discuss
[CS M51A W13] Assignment 6
Due: 03/15/13
TA: Gabriel Pan ([email protected])
Homework Problems (35 points total)
Problem 1 (6 points)
We would like to put together a 12-input decoder using 4-input decoders. Let us consider the following two
methods.
1. Us
[CSM51A W12] Assignment 1
Assigned: 01/13/12, Due: 01/20/12
TAs: Neil Conos ([email protected]), Gabriel Pan ([email protected])
Rules of Engagement: Exercises are for your practicesolutions are provided so you can check your
work. Homework problems must
[CSM51A W12] Solution to Assignment 1
Assigned: 01/13/12, Due: 01/20/12
TAs: Neil Conos ([email protected]), Gabriel Pan ([email protected])
Homework Problems (50 points total)
Problem 1 (10 points)
A multiplexor (MUX) is a 3-input function z (x, y, sel)
[CSM51A W12] Assignment 2
Assigned: 01/27/12, Due: 02/03/12
TAs: Neil Conos ([email protected]), Gabriel Pan ([email protected])
Rules of Engagement: Exercises are for your practicesolutions are provided so you can check your
work. Homework problems must
[CS M51A Winter 12] Solution to Assignment 4
Assigned: 02/18/12, Due: 02/24/12
TAs: Neil Conos ([email protected]), Gabriel Pan ([email protected])
Homework Problems (70 points total)
Problem 1 (15 points)
A system is described by the following table. Min
[CS M51A Winter 12] Assignment 3
Assigned: 02/03/12, Due: 02/10/12
TAs: Neil Conos ([email protected]), Gabriel Pan ([email protected])
Rules of Engagement: Exercises are for your practicesolutions are provided so you can check your
work. Homework problem
[CSM51A W12] Solution to Assignment 2
Assigned: 01/27/12, Due: 02/03/12
TAs: Neil Conos ([email protected]), Gabriel Pan ([email protected])
Homework Problems (50 points total)
Problem 1 (10 points)
We are given the following design of a complex CMOS gate
NAME
First
Last
Student ID#
UNIVERSITY OF CALIFORNIA
LOS ANGELES
COMPUTER SCIENCE DEPARTMENT
MIDTERM EXAMINATION #1
CSM51A/EEM16
Fall Quarter 2005
November 23, 2005
This is a closed-book exam. (100 minutes)
Use this form for your work and return it.
The e
SPECIFICATION OF SEQUENTIAL SYSTEMS
1
Synchronous sequential systems
Mealy and Moore machines
Time behavior
State minimization
Introduction to Digital Systems
7 cfw_ Speci cation of Sequential Systems
De nition
2
z (t) = F (x(0; t)
x
x(t)
z
z(t)
time
t
Fi
1
SEQUENTIAL NETWORKS
Canonical form of sequential networks
Latches and edge-triggered cells. D ip- op
Set-up time, hold time, and propagation delay
Analysis and design of canonical networks
SR, JK and T ip- op
Analysis of ip- op networks
Design of ip- op
ARITHMETIC COMBINATIONAL MODULES AND NETWORKS
1
Speci cation of adder modules for positive integers
Half-adder and full-adder modules
Carry-ripple and carry-lookahead adder modules
Networks of adder modules
Representation of signed integers: sign-and-magn
STANDARD SEQUENTIAL MODULES
Registers
Shift registers
Synchronous counters
For each module we show:
Its speci cation
An implementation with ip- ops and gates
Its basic uses
Ways of implementing larger modules with smaller ones
Introduction to Digital Syst
PROGRAMMABLE MODULES
1
Speci cation of programmable combinational and sequential modules
1. psa
2. rom
3. fpga
The way the modules are programmed
Networks of programmable modules
Examples of uses
Introduction to Digital Systems
12 cfw_ Programmable Module
CS M51A / EE M16
Winter 2011
Homework #3
Problem 1) Determine the state diagram and state table for the sequential system which
outputs a 1 when the input sequence does NOT contain the sequence 1-0.
Problem 2) Determine the state diagram and state table f
CS M51A / EE M16
Winter 2011
Homework #4
Problem 1: Design each code converter using a decoder and OR gates. (Only 1 part
would appear on the quiz)
a. BCD to seven-segment code
b. 4-bit binary to 4-bit Gray code
Problem 2: Design a combinational network t
SPECIFICATION OF COMBINATIONAL SYSTEMS
1
High-level and binary-level speci cations.
Representation of data elements (signal values) by binary variables (signals) and standard
codes for positive integers and characters.
Representation by switching function
DESCRIPTION AND ANALYSIS OF GATE NETWORKS
1
Gate networks
Sets of gates: (AND OR NOT), NAND NOR XOR
Analysis and description of gate networks
Introduction to Digital Systems
4 cfw_ Gate Networks: Description and Analysis
2
Combinational system
Combination
UNIVERSITY OF CALIFORNIA
LOS ANGELES
COMPUTER SCIENCE DEPARTMENT
MIDTERM EXAMINATION - SOLUTIONS
CS M51A
Winter Quarter 2003
February 3, 2002
MIDTERM SOLUTIONS
1
CSM51A/EEM16
February 5, 2002
Find x, y, and z such that the following conditions are satised
Name
First
Last
Student ID #
University of California
Los Angeles
Computer Science Department
CSM51A Midterm Exam #2
Fall Quarter 2008
November 13rd 2008
This is a closed book exam. Absolutely nothing is permitted except pen, pencil and
eraser to write yo
NAME_
First
Last
STUDENT ID #_
UNIVERSISTY OF CALIFORNIA
LOS ANGELES
COMPUTER SCIENCE DEPT.
MIDTERM EXAMINATION #2
CSM51A / EEM16
Fall Quarter 2007
Nov 20th, 2007
This is a closed-book exam. (100 minutes)
The exam has 6 problems. All problems will be grad