[CS M51A Winter 10] Assignment 6
Assigned: 03/09/12, Due: 03/16/12
TAs: Neil Conos ([email protected]), Gabriel Pan ([email protected])
Rules of Engagement: Homework problems must be submitted on the
-So\ut;an
NAME
First
Last
Student ID#
UNIVERSITY OF CALIFORNIA
LOS ANGELES
COMPUTER SCIENCE DEPARTMENT
MIDTERM EXAMINATION #l
CSM51A/EEM16
Fall Quarter 2005
November 2, 2005
This is a closed-book exam
UNIVERSITY OF CALIFORNIA
LOS ANGELES
COMPUTER SCIENCE DEPARTMENT
MIDTERM EXAMINATION - SOLUTIONS
CS M51A
Fall Quarter 2002
October 24, 2002
MIDTERM SOLUTIONS
1
CSM51A/EEM16
October 24, 2002
Find x, y,
CS M51A / EE M16
Winter 2011
Homework #5
Problem 1: Implement the following program repeatedly using a single 8-bit
adder/subtracter (AS) module, 8-bit registers, as few as possible as small as possib
[CS M51A Winter 12] Assignment 4
Assigned: 02/18/12, Due: 02/24/12
TAs: Neil Conos ([email protected]), Gabriel Pan ([email protected])
Rules of Engagement: Homework problems must be submitted on the
[CS M51A Winter 12] Solution to Assignment 5
Assigned: 03/02/12, Due: 03/09/12
TAs: Neil Conos ([email protected]), Gabriel Pan ([email protected])
Homework Problems (50 points total)
Problem 1 (10 po
[CS M51A Winter 12] Solution to Assignment 4
Assigned: 02/18/12, Due: 02/24/12
TAs: Neil Conos ([email protected]), Gabriel Pan ([email protected])
Homework Problems (70 points total)
Problem 1 (15 po
[CS M51A W13] Assignment 6
Due: 03/15/13
TA: Gabriel Pan ([email protected])
Homework Problems (35 points total)
Problem 1 (6 points)
We would like to put together a 12-input decoder using 4-input dec
[CSM51A W12] Assignment 1
Assigned: 01/13/12, Due: 01/20/12
TAs: Neil Conos ([email protected]), Gabriel Pan ([email protected])
Rules of Engagement: Exercises are for your practicesolutions are provi
[CSM51A W12] Solution to Assignment 1
Assigned: 01/13/12, Due: 01/20/12
TAs: Neil Conos ([email protected]), Gabriel Pan ([email protected])
Homework Problems (50 points total)
Problem 1 (10 points)
A
[CSM51A W12] Assignment 2
Assigned: 01/27/12, Due: 02/03/12
TAs: Neil Conos ([email protected]), Gabriel Pan ([email protected])
Rules of Engagement: Exercises are for your practicesolutions are provi
[CS M51A Winter 12] Assignment 5
Assigned: 03/02/12, Due: 03/09/12
TAs: Neil Conos ([email protected]), Gabriel Pan ([email protected])
Rules of Engagement: Homework problems must be submitted on the
[CS M51A Winter 12] Assignment 3
Assigned: 02/03/12, Due: 02/10/12
TAs: Neil Conos ([email protected]), Gabriel Pan ([email protected])
Rules of Engagement: Exercises are for your practicesolutions ar
[CS M51A Winter 12] Solution to Assignment 3
Assigned: 02/03/12, Due: 02/10/12
TAs: Neil Conos ([email protected]), Gabriel Pan ([email protected])
Homework Problems (70 points total)
Problem 1 (20 po
[CSM51A W12] Solution to Assignment 2
Assigned: 01/27/12, Due: 02/03/12
TAs: Neil Conos ([email protected]), Gabriel Pan ([email protected])
Homework Problems (50 points total)
Problem 1 (10 points)
W
NAME
First
Last
Student ID#
UNIVERSITY OF CALIFORNIA
LOS ANGELES
COMPUTER SCIENCE DEPARTMENT
MIDTERM EXAMINATION #1
CSM51A/EEM16
Fall Quarter 2005
November 23, 2005
This is a closed-book exam. (100 mi
SPECIFICATION OF SEQUENTIAL SYSTEMS
1
Synchronous sequential systems
Mealy and Moore machines
Time behavior
State minimization
Introduction to Digital Systems
7 cfw_ Speci cation of Sequential Systems
1
SEQUENTIAL NETWORKS
Canonical form of sequential networks
Latches and edge-triggered cells. D ip- op
Set-up time, hold time, and propagation delay
Analysis and design of canonical networks
SR, JK an
STANDARD COMBINATIONAL MODULES
Decoders
Encoders
Multiplexers (Selectors)
Demultiplexers (Distributors)
Shifters
Introduction to Digital Systems
9 cfw_ Standard Combinational Modules
1
Binary decoders
ARITHMETIC COMBINATIONAL MODULES AND NETWORKS
1
Speci cation of adder modules for positive integers
Half-adder and full-adder modules
Carry-ripple and carry-lookahead adder modules
Networks of adder m
STANDARD SEQUENTIAL MODULES
Registers
Shift registers
Synchronous counters
For each module we show:
Its speci cation
An implementation with ip- ops and gates
Its basic uses
Ways of implementing larger
PROGRAMMABLE MODULES
1
Speci cation of programmable combinational and sequential modules
1. psa
2. rom
3. fpga
The way the modules are programmed
Networks of programmable modules
Examples of uses
Intr
CS M51A / EE M16
Winter 2011
Homework #3
Problem 1) Determine the state diagram and state table for the sequential system which
outputs a 1 when the input sequence does NOT contain the sequence 1-0.
P
CS M51A / EE M16
Winter 2011
Homework #4
Problem 1: Design each code converter using a decoder and OR gates. (Only 1 part
would appear on the quiz)
a. BCD to seven-segment code
b. 4-bit binary to 4-bi
SPECIFICATION OF COMBINATIONAL SYSTEMS
1
High-level and binary-level speci cations.
Representation of data elements (signal values) by binary variables (signals) and standard
codes for positive intege
DESCRIPTION AND ANALYSIS OF GATE NETWORKS
1
Gate networks
Sets of gates: (AND OR NOT), NAND NOR XOR
Analysis and description of gate networks
Introduction to Digital Systems
4 cfw_ Gate Networks: Desc
UNIVERSITY OF CALIFORNIA
LOS ANGELES
COMPUTER SCIENCE DEPARTMENT
MIDTERM EXAMINATION - SOLUTIONS
CS M51A
Winter Quarter 2003
February 3, 2002
MIDTERM SOLUTIONS
1
CSM51A/EEM16
February 5, 2002
Find x,
Name
First
Last
Student ID #
University of California
Los Angeles
Computer Science Department
CSM51A Midterm Exam #2
Fall Quarter 2008
November 13rd 2008
This is a closed book exam. Absolutely nothing
NAME_
First
Last
STUDENT ID #_
UNIVERSISTY OF CALIFORNIA
LOS ANGELES
COMPUTER SCIENCE DEPT.
MIDTERM EXAMINATION #2
CSM51A / EEM16
Fall Quarter 2007
Nov 20th, 2007
This is a closed-book exam. (100 minu