201A VLSI Design Automation
Prof. Lei He
[email protected]
Chapter Outline
Fault modeling
Logic simulation
Basics of ATPG
ATPG for combinational circuits
(with slides adopted from Prof. Kewal Saluja
at University of Wisconsin)
06/25/15
2
Overview
Major ATPG
EE 201A
Fundamentals to Computer-Aided Design of
VLSI Circuits and Systems
Instructor:
Lei He
Email:
[email protected]
Outline
Course Logistics and Overview
Introduction to circuit platforms
Instructor Info
Email: [email protected]
Office hours: MW 6-7, BH673
EE 201A
Winter 2015
Final Project
DUE: Before March 22nd 23:59
Problem:
Given two 4x4 matrixes A and B, where matrix A can be any integer value
and matrix B is a constant matrix as Fig. 1 shows, design a matrix multiplier
module that performs matrix multi
Power Minimization for Testing
Roy
[email protected]
Outline
Design for Testability
Scan Testing
Testing Power Minimization
Testing for Sequential Circuit
Sequential ATPG
Poor controllability
What is Design for Testability (DFT)
Insert circuitry tha
EE 201A
Winter 2015
Final Project
DUE: Before March 22nd 23:59
Problem:
You will be working under the maze_partial folder. You goal is to finish the routing algorithms
based on the existing code. The init file is an example of a test case. It defines the
Homework #2 solution
Problem 1:
Due to the duality of the thermal and electrical models, the solution can be
interpreted as a circuit analysis.
The temperature of the two nodes, TCPU and TBOX can be presented as
VTCPU (noted as V1) and VTBOX (noted as V2)
EE 201A
Winter 2015
HOMEWORK #5
Due: March 20th
Note: For every problem listed, please show step by step solution.
Problem 1: Fault collapsing
For the following circuit,
A. What is the number of all potential single stuck-at faults?
B. Derive the equivale
EE 201A
Winter 2015
HOMEWORK #2
Due: Feb 1st, 15
Note: For every problems listed below, please write down and show step by
step calculation.
Problem 1: Temperature Calculation
A simple example with the thermal characteristics of the
CPU,
box
(entire
compu
Homework #2 solution
Problem 1:
Assuming the two partition are named A and B. Consider any node a in the
partition A, the external cost of a is denoted as Ea, where
=
The internal cost of the node Ia is defined as the following:
=
Moving the node a fr
EE 201A
Winter 2015
HOMEWORK #3
DUE: Feb 22nd
Note: For every problems listed below, please write down and show step by
step calculation.
Problem 1: Partitioning
Consider the gate-level circuit shown in Figure 1(a). Figure 1(b) shows an
undirected graph m
201A VLSI Design Automation
Prof.LeiHe
[email protected]
Chapter Outline
Fault modeling
Logic simulation
Basics of ATPG
ATPG Algorithms for combinational circuits
(with slides adopted from Prof. Kewal Saluja
at University of Wisconsin)
06/25/15
2
Overview
S
Partitioning and
Clustering
Professor Lei He
[email protected]
http:/eda.ee.ucla.edu/
Chapter 3 Physical
Design
Static timing analysis
Partitioning and clustering
Floorplanning and placement
Routing and interconnect
optimization
Outline
Circuit Partitioning
Chapter3PhysicalDesign
ProfessorLeiHe
[email protected]
http:/eda.ee.ucla.edu/
Outline
Static timing analysis
Partitioning and clustering
Floorplanning
Moduleorientationproblem
Slicingfloorplandesign
Placement and routing
Floorplanning
Given , for each bloc
UCLA EE209A 2005
Professor Lei He
Physical Design (II)
Thanks to Chris Chu, Jason Cong, Paul Villarubia and David Pan for contributions to slides
06/25/15
1
Outline
STA
Partitioning
Floorplanning
Placement
Routing and buffer insertion
06/25/15
2
Prob
201A VLSI Design Automation
Prof.LeiHe
2008Spring
Chapter 5
Testing and (Formal) Verification
Fault modeling
Logic simulation
Basics of ATPG
ATPG Algorithms for combinational circuits
Student presentation
BDD and its application to formal verification
(w
UCLAEE201AProfessorLeiHe
StaticTimingAnalysis
Chapter3PhysicalDesign
Static timing analysis
Partitioning and clustering
Floorplanning and placement
Routing and interconnect
optimization
StaticTimingAnalysis(STA)
PartI
Motivation
Givenagatelevelnetlist
Its
EE201C Chapter2
Power and Thermal Modeling
Prof. Lei He
[email protected]
Reading Assignments
V. Tiwari, D. Singh, S. Rajgopal, G. Mehta, R. Patel, and F. Baez,
Reducing power in high-performance microprocessors," in ACM/IE
EE DAC, 1998
K. Skadron, et al, T
High-Quality, Deterministic Par
allel Placement for FPGAs
Fang Gong
Part of the slides are from Vaughn Betzs presentation on FPGA08;
The figures or tables from his presentation will be marked with
asterisk(*)
Outline
Background
Execution Environment Defin
EE201A: Fundamentals of ComputerAided Design of VLSI Circuits and
Systems
Puneet Gupta
Some notes adopted from
Andrew B. Kahng
Lei He
Igor Markov
Mani Srivastava
Puneet Gupta ([email protected])
[email protected]
Instructor Info
Puneet Gupta
http:/na
Partitioning
Some contributions from
Lei He
Andrew B. Kahng
Igor Markov
Mohammad Tehranipoor
Puneet Gupta ([email protected])
Logistics
Reading for this week uploaded on Piazza
Cycle stealing: i.e., STA in presence of latches
TODAY
Partitioning
Punee