Lecture 3: Logic Synthesis
EE201A
Some notes adopted from
Andrew B. Kahng
Lei He
Igor Markov
Mani Srivastava
Synopsys
Various Sources
Puneet Gupta ([email protected])
Logistics
Lab 1 has been posted
Physical Design (Routing)
Professor Lei He
[email protected]
http:/eda.ee.ucla.edu/
Outline
VLSI Design Flow
Partitioning
Floorplanning
Placement
Routing
15/6/25
2
Routing
Overview and the Flow
Fundamen
201A VLSI Design Automation
Prof. Lei He
[email protected]
Chapter Outline
Fault modeling
Logic simulation
Basics of ATPG
ATPG for combinational circuits
(with slides adopted from Prof. Kewal Saluja
at
EE 201A
Fundamentals to Computer-Aided Design of
VLSI Circuits and Systems
Instructor:
Lei He
Email:
[email protected]
Outline
Course Logistics and Overview
Introduction to circuit platforms
Instructor
EE 201A
Winter 2015
Final Project
DUE: Before March 22nd 23:59
Problem:
Given two 4x4 matrixes A and B, where matrix A can be any integer value
and matrix B is a constant matrix as Fig. 1 shows, desig
Power Minimization for Testing
Roy
[email protected]
Outline
Design for Testability
Scan Testing
Testing Power Minimization
Testing for Sequential Circuit
Sequential ATPG
Poor controllability
Wha
EE 201A
Winter 2015
Final Project
DUE: Before March 22nd 23:59
Problem:
You will be working under the maze_partial folder. You goal is to finish the routing algorithms
based on the existing code. The
Homework #2 solution
Problem 1:
Due to the duality of the thermal and electrical models, the solution can be
interpreted as a circuit analysis.
The temperature of the two nodes, TCPU and TBOX can be p
EE 201A
Winter 2015
HOMEWORK #5
Due: March 20th
Note: For every problem listed, please show step by step solution.
Problem 1: Fault collapsing
For the following circuit,
A. What is the number of all p
EE 201A
Winter 2015
HOMEWORK #2
Due: Feb 1st, 15
Note: For every problems listed below, please write down and show step by
step calculation.
Problem 1: Temperature Calculation
A simple example with th
Homework #2 solution
Problem 1:
Assuming the two partition are named A and B. Consider any node a in the
partition A, the external cost of a is denoted as Ea, where
=
The internal cost of the node I
EE201C Chapter2
Power and Thermal Modeling
Prof. Lei He
[email protected]
Reading Assignments
V. Tiwari, D. Singh, S. Rajgopal, G. Mehta, R. Patel, and F. Baez,
Reducing power in high-performance microp
Lecture 8: Placement
EE201A
Some notes adopted from
Andrew B. Kahng
Lei He
Igor Markov
Mani Srivastava
Mohammad Tehranipoor
Puneet Gupta ([email protected])
Logistics
No HW this week
Placement read
Lecture 12: Test
EE201A
Puneet Gupta ([email protected])
Some notes adopted from
Andrew B. Kahng
Lei He
Sandeep Gupta
Alexandre Schmid
Synopsys
Logistics
Project:
Midterm report due TODAY
Quiz 2 o
Partitioning and
Clustering
Professor Lei He
[email protected]
http:/eda.ee.ucla.edu/
Chapter 3 Physical
Design
Static timing analysis
Partitioning and clustering
Floorplanning and placement
Routing and
UCLA EE209A 2005
Professor Lei He
Physical Design (II)
Thanks to Chris Chu, Jason Cong, Paul Villarubia and David Pan for contributions to slides
06/25/15
1
Outline
STA
Partitioning
Floorplanning
EE 201A
Winter 2015
HOMEWORK #3
DUE: Feb 22nd
Note: For every problems listed below, please write down and show step by
step calculation.
Problem 1: Partitioning
Consider the gate-level circuit shown
Lecture 7: Floorplanning
EE201A
Some notes adopted from
Andrew B. Kahng
Lei He
Igor Markov
Mani Srivastava
Mohammad Tehranipoor
Puneet Gupta ([email protected])
Introduction
System Specification
Part
R
Foundations and Trends
in
Electronic Design Automation
Vol. 6, No. 1 (2012) 1120
c 2012 J. Lee and P. Gupta
DOI: 10.1561/1000000019
Discrete Circuit Optimization: Library
Based Gate Sizing and Thres
Lecture 4: Logic Synthesis -2
EE201A
Some notes adopted from
Andrew B. Kahng
Lei He
Igor Markov
Mani Srivastava
Synopsys
Various Sources
Puneet Gupta ([email protected])
Logistics
Students should he
Static Timing Analysis
(STA)
Some contributions from
Lei He
Andrew B. Kahng
Puneet Gupta ([email protected])
Logistics
Lab2 uploaded on Piazza
A guide from UCSD on how to use CAD tools
effectively
Partitioning
Some contributions from
Lei He
Andrew B. Kahng
Igor Markov
Mohammad Tehranipoor
Puneet Gupta ([email protected])
Logistics
Reading for this week uploaded on Piazza
Cycle stealing: i.e.