UCLA
Department of Electrical Engineering
EEM16 Spring 2009
Homework 5
Due May 21st, 2009
1. Clock Analysis: Given the sequential-logic circuit shown below, where the
latches have worst-case setup times of 20 ns, propagation delays of 13 ns, hold
times of

Electrical Engineering Department
EEM16
Logic Design of Digital Systems
Course Syllabus
Week
1
2
3
4
5
6
7
8
9
10
Textbook:
Fall 2013
Prof. Danijela Cabric
danijela@ee.ucla.edu
Date
Day
Lecture
Due
Sep 28
Mon
Introduction about Digital Systems
Ch. 1
Sep 3

EEM16/CSM51A:
Logic Design of Digital Systems
Lecture #10
Sequential Circuits
Prof. Danijela Cabric
Fall 2015
Sequential logic has state
i
n
C
L
o
m
Combinational Logic
State captures relevant
information about the past
(c) 2005-2012 W. J. Dally
2
Specify

EEM16/CSM51A:
Logic Design of Digital Systems
Lecture #11
Sequential Circuits and Modules
Prof. Danijela Cabric
Fall 2013
Midterm statistics
2
Special State Assignment
One FF per state
3
Primitive for One FF per state
4
Example: A Traffic-Light Controller

EEM16/CSM51A:
Logic Design of Digital Systems
Lecture #1
Introduction
Prof. Danijela Cabric
Fall 2015
Course Staf
Instructor: Danijela Cabric
Associate Professor in EE Department
Email: danijela@ee.ucla.edu
Office: 56-147C Eng. IV
Office Hours: Tue 3:30p

EEM16/CSM51A:
Logic Design of Digital Systems
Lecture #7
Arithmetic Circuits
Prof. Danijela Cabric
Fall 2015
Numbers
Digital logic works with binary numbers
Each bit has a value based on its position
(c) 2005 - 2012 W. J. Dally
2
From Decimal To Binary

EEM16/CSM51A:
Logic Design of Digital Systems
Lecture #4
Design of Combinational Systems
Prof. Danijela Cabric
Fall 2015
Graphical Representation of Switching
Functions: Karnaugh Maps (or K-Maps)
2-dimensional arrays of cells represent switching
function

EEM16/CSM51A:
Logic Design of Digital Systems
Lecture #5
Combinational Building Blocks
Prof. Danijela Cabric
Fall 2015
Recap of class thus far
Introduction of digital design
Digital representation
Boolean Algebra
Combinational logic design
Truth table

EEM16/CSM51A:
Logic Design of Digital Systems
Lecture #3
Design of Combinational Systems
Prof. Danijela Cabric
Fall 2015
Set representation of Switching Functions
2
Normal Form
Sum of Products (SoP) Form
3
Minterm
For a Boolean function of n variables x1

EEM16/CSM51A:
Logic Design of Digital Systems
Lecture #2
Boolean Algebra
Prof. Danijela Cabric
Fall 2015
Two Classes of Digital Systems
Combinational Systems
Output at time t depends only on the
input at time t
i.e. no memory
z(t) = F(x(t)
Sequential

EE M16: Logic Design of Digital Systems
Fall 2015
Assignment #1 Solutions
Instructor: Prof. Danijela Cabric
Scribe: Ghaith Hattab
Exercise 1.11 (Encoding playing cards)
For both (a) and (b) we can use a 6-bit scheme where the top 2 bits represent the suit

EE M16: Logic Design of Digital Systems
Fall 2015
Assignment #6 due Wednesday, December 2, 2015
Instructor: Prof. Danijela Cabric
Scribe: Mihir Laghate
Exercise 14.30 (Direction sensor, I.). A direction sensor is used to detect the direction of a rotating

EE M16: Logic Design of Digital Systems
Fall 2015
Assignment #4 due Monday, November 9, 2015
Instructor: Prof. Danijela Cabric
Scribe: Ghaith Hattab
Important Note: The HW should be submitted in CORES lab 54-130B in Eng. IV between 10am and 12pm
on Monday

EE M16: Logic Design of Digital Systems
Fall 2015
Assignment #2 due Monday, October 19, 2015
Instructor: Prof. Danijela Cabric
Scribe: Mihir Laghate
Exercise 6.8 (Combinational design). Design a minimal CMOS circuit that implements the function f =
m(3, 4

EE M16: Logic Design of Digital Systems
Fall 2015
Assignment #3 due Monday, October 26, 2015
Instructor: Prof. Danijela Cabric
Scribe: Ghaith Hattab
Exercise A1 (Multiplexer ).
(a) How many 4-input multiplexers are needed to implement a 256-input multiple

VHDL Intro 1
EEM16 Spring08
Background
Hardware Description Language
Standard language for documentation and automation of
design process in computer systems
VHDL stands for VHSIC: Very High Speed
Integrated Circuit Hardware Description
Language
USA D

UCLA
Department of Electrical Engineering
EEM16 Spring 2009
Homework 4
Due May 14th, 2009
1. State Minimization: Given the state diagram in figure below, determine which
states should be combined to determine the reduced state diagram.
2. Reverse engineer

EEM16/CSM51A:
Logic Design of Digital Systems
Lecture #6
Arithmetic Circuits
Prof. Danijela Cabric
Fall 2015
Numbers
Digital logic works with binary numbers
Each bit has a value based on its position
(c) 2005 - 2012 W. J. Dally
2
From Decimal To Binary