CSM51A Homework 3 UCLA
TAs: Pouya Dormiani, Gabriel Pan [email protected], [email protected] Assigned: Friday 10/12/07 Due: Friday 10/19/07 Problem 1
Using the postulates of Boolean algebra and the theorems given in the Appendix, prove that a b + ab
BOOLEAN ALGEBRAS Important class of algebras extensively used for many purposes
1
Basis of the switching algebra (SA) for formal treatment of switching circuits: Transformation of switching expressions Identities from BA enable graphical and ta
194
Solutions Manual - Introduction to Digital Design - November 15, 2000
Exercise 10.4 BCD Addition When we add two BCD digits (0.9), considering a carry-in bit, the range of values obtained is from 0 to 19. The output consists of a carry out and
120
Exercise 8.2:
Solutions Manual - Introduction to Digital Design - November 2, 2000
Using the notation given on Figure 8.15 of the textbook we obtain the following network parameters: Combinational Networks' delays:
d
1x = d1y = 4 tp (gate) = 2
Solutions Manual - Introduction to Digital Design - November 2, 2000
Exercise 7.4
103
The state diagram for this exercise is shown in Figure 7.2 on page 103.
a/0
a/0 c/0 b/1 A c/1 b/1 c/1 E b/1 a/0 c/0 D
B b/1
c/1 b/1
C
a/0
a/0
Figure 7.2: S
CSM51A Homework 2 UCLA
TAs: Pouya Dormiani, Gabriel Pan [email protected], [email protected] Assigned: Friday 10/05/07 Due: Friday 10/12/07 Problem1
Simplify a + a b + a b c + a b c d + a b c d
Problem2
The XOR operator is denoted by the symbol an
CSM51A Homework 1 UCLA
TAs: Pouya Dormiani, Gabriel Pan [email protected], [email protected] Assigned: Monday 10/01/07 Due: Friday 10/05/07 Problem 1
A useful switching function is the majority switching function, defined by the following expression
CS MélA/EE Ml FINAL EXAM
* Closed books and notes ~
(8 problema 180 minutes)
PLEASE BE SYSTEMATIC, ORGANIZED, and NEAT:
* this will be considered in the grading.
December 137 2002.
Mwa
Name;
Problem Points Score
1
1 CS M51A/EE M16 FINAL EXAM { closed books and notes { (8 problems, 180 minutes) December 13, 2002
PLEASE BE SYSTEMATIC, ORGANIZED, and NEAT:
{ this will be considered in the grading.
Name:
Problem Points Score 1 20 2 10 3 14 4 12 5 8 6 13 7 13 8
DESCRIPTION AND ANALYSIS OF GATE NETWORKS
1
GATE NETWORKS SETS OF GATES: (AND OR NOT), NAND NOR XOR ANALYSIS AND DESCRIPTION OF GATE NETWORKS
Introduction to Digital Systems
4 Gate Networks: Description and Analysis
2
Combinational system
COMBINATIONAL ICs
REPRESENTATION OF BINARY VARIABLES AT THE PHYSICAL LEVEL BASIC SWITCH. STRUCTURE OF GATES AND THEIR OPERATION REALIZATION OF GATES USING cmos CIRCUITS
1
CHARACTERISTICS OF CIRCUITS: LOAD FACTORS AND FANOUT FACTORS, PROPAGATION
SPECIFICATION OF COMBINATIONAL SYSTEMS
HIGH-LEVEL AND BINARY-LEVEL SPECIFICATIONS
1
REPRESENTATION OF DATA ELEMENTS BY BINARY VARIABLES; STANDARD CODES FOR POSITIVE INTEGERS AND CHARACTERS REPRESENTATION BY SWITCHING FUNCTIONS AND SWITCHING EXPR
INTRODUCTION TO DIGITAL SYSTEMS DESCRIPTION AND DESIGN OF DIGITAL SYSTEMS FORMAL BASIS: SWITCHING ALGEBRA IMPLEMENTATION: MODULES (ICs) AND NETWORKS IMPLEMENTATION OF ALGORITHMS IN "HARDWARE" COURSE EMPHASIS: CONCEPTS, ANALYSIS AND DESIGN Follo
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192
Exercise 9.22
Solutions Manual - Introduction to Digital Design - November 15, 2000 Considering the network formed by the decoder and the multiplexer we have that ( 1 if (w; d; e) = (f; g; h) z = 0 otherwise
(9:6)
where w is the output of the