Discussion 3 Problems and Solutions
Wei Wu, Tianheng Tu, Babak Daneshrad
24 October 2014
All the problems are taken from the class textbook (Dally & Harting). The
appropriate problem number from the textbook is noted in brackets.
1
Problem 1 (6.11)
Design
all 2013, EEM16: Logic Design of Digital Systems
Homework #4 problems
Due date: Dec. 5th
Homework problems can be found on textbook: Digital Design: A Systems
Approach by William James Dally and R. Curtis Harting
Please write your
EEM16: Logic Design of Digital Systems
Discussion #4 problems
1. Implement the function f(a,b,c,d) = one-set(1.3.4.9.14.15) using
a. An eight-input multiplexer;
b. An four-input multiplexer and NOR gates(use inputs a and b as select inputs to the
multiple
UCLA
Department of Electrical Engineering
EEMl6 Fall 2012 J" V1 Mn'
Midterm
October 30, 2012 gammy.
(The midterm contains 6 problems)
Exam is closed book. You are allowed one 8 V: x ll double-sided cheat sheet.
Calculators are allowed.
Show the intermedia
EE M16: Logic Design of Digital Systems
Fall 2015
Assignment #1 due Monday, October 12, 2015
Instructor: Prof. Danijela Cabric
Scribe: Ghaith Hattab
Exercise 1.11 (Encoding playing cards). Suggest a binary representation for playing cards a set of
binary
Exercise 7.22
A sequential system has a decimal digit as input and a radix-5 digit as output. The output
counts modulo-5 the number of times the pattern 358 has occurred in x(0, t). Give a state
description of the system. Hint: Decompose the system into t
EEM16: Logic Design of Digital Systems
Discussion #8 problems
1. Implement a sequential (bit-serial) binary adder/subtracter. A control input k indicates
whether an addition (k=1) or a subtraction (k=0) is performed.
2. A combinational lock opens when the
UCLA
Department of Electrical Engineering
EEM16 Fall 2011
Final Exam
December 7, 2011
(The final contains 7 problems)
1.
2.
3.
4.
Exam is closed book. You are allowed two 8 x 11 double-sided cheat sheet.
Calculators are allowed.
Show the intermediate step
Discussion 2 Problems and Solutions
Wei Wu, Tianheng Tu, Babak Daneshrad
17 October 2014
All the problems are taken from the class textbook (Dally & Harting). The
appropriate problem number from the textbook is noted in brackets.
1
Problem 1 (3.6)
De Morg
EEM16: Logic Design of Digital Systems
Discussion #4 solutions
1. Implement the function f(a,b,c,d) = one-set(1.3.4.9.14.15) using
a. An eight-input multiplexer;
b. An four-input multiplexer and NOR gates(use inputs a and b as select inputs to the
multipl
EEM16: Logic Design of Digital Systems
Discussion #8 Solutions
1. Implement a sequential (bit-serial) binary adder/subtracter. A control input k indicates
whether an addition (k=1) or a subtraction (k=0) is performed.
2. A combinational lock opens when th
EEM16/CSM51A: Logic Design of Digital Systems
Module #8: Sequential Logic FSMs
C.K. Yang
[email protected]
Notes attributed to
Srivastava (UCLA), Mitra & Dally (Stanford)
Copyright (c) 2017
HENRY SAMUELI SCHOOL OF ENGINEERING AND APPLIED SCIENCE
ELECTRICAL
Discussion #9 Problems and Solutions
CSM51A / EEM16 Spring 2017
June 2, 2017
Problems labeled with Textbook tags are taken from the class textbook (Dally & Harting).
1
[Warmup] Timing Values
Somehow the engineer youre working with misplaced the labels for
Discussion #8 Problems and Solutions
CSM51A / EEM16 Spring 2017
May 26, 2017
Problems labeled with Textbook tags are taken from the class textbook (Dally & Harting).
[Warmup]
Q: What is the difference between a traditional FSM and a Datapath FSM?
Q: What
EEM16/CSM51A: Logic Design of Digital Systems
Module #1: Course Introduction
C.K. Yang
[email protected]
Notes attributed to
Srivastava (UCLA), Mitra & Dally (Stanford)
Copyright (c) 2017
HENRY SAMUELI SCHOOL OF ENGINEERING AND APPLIED SCIENCE
ELECTRICAL EN
Discussion #7 Problems and Solutions
CSM51A / EEM16 Spring 2017
May 19, 2017
Problems labeled with Textbook tags are taken from the class textbook (Dally & Harting).
[Example] Multi-model counter
a. Draw the FSM for a multi-model counter with 3-bit states
EEM16/CSM51A: Logic Design of Digital Systems
Module #8: Sequential Logic
C.K. Yang
[email protected]
Notes attributed to
Srivastava (UCLA), Mitra & Dally (Stanford)
Copyright (c) 2017
HENRY SAMUELI SCHOOL OF ENGINEERING AND APPLIED SCIENCE
ELECTRICAL ENGIN
EEM16/CSM51A: Logic Design of Digital Systems
Module #5: Combinational Logic Design
C.K. Yang
[email protected]
Notes attributed to
Srivastava (UCLA), Mitra & Dally (Stanford)
Copyright (c) 2017
HENRY SAMUELI SCHOOL OF ENGINEERING AND APPLIED SCIENCE
ELECTR
EEM16/CSM51A: Logic Design of Digital Systems
Module #4: Boolean Algebra
C.K. Yang
[email protected]
Notes attributed to
Srivastava (UCLA), Mitra & Dally (Stanford)
Copyright (c) 2017
HENRY SAMUELI SCHOOL OF ENGINEERING AND APPLIED SCIENCE
ELECTRICAL ENGINE
EEM16/CSM51A: Logic Design of Digital Systems
Module #6: Combinational Building Blocks
C.K. Yang
[email protected]
Notes attributed to
Srivastava (UCLA), Mitra & Dally (Stanford)
Copyright (c) 2017
HENRY SAMUELI SCHOOL OF ENGINEERING AND APPLIED SCIENCE
ELE
EEM16/CSM51A: Logic Design of Digital Systems
Module #8: Sequential Logic - Design Procedure
and Examples
C.K. Yang
[email protected]
Notes attributed to
Srivastava (UCLA), Mitra & Dally (Stanford)
Copyright (c) 2017
HENRY SAMUELI SCHOOL OF ENGINEERING AND
Discussion #5 Problems and Solutions
CSM51A / EEM16 Spring 2017
May 5, 2017
Problems labeled with Textbook tags are taken from the class textbook (Dally & Harting).
[Textbook 10.1] Decimal to binary conversion, I.
Convert 817 from decimal to binary notati
UCLA | EEM16/CSM51A | Spring 2017
Prof. C.K. Yang
Homework #3
(Deadline: 11:59PM PDT, Sunday, May 21, 2017)
Name (Last, First):
Student Id #:
INSTRUCTIONS
This homework is to be done individually. You may use any tools or refer to published papers or
Discussion #2 Problems and Solutions
CSM51A / EEM16 Spring 2017
April 14, 2017
Problems labeled with Textbook tags are taken from the class textbook (Dally & Harting).
[Textbook 3.13] Dual Functions, I
Find the dual of the following function and write it
UCLA | EEM16/CSM51A | Spring 2017
Prof. C.K. Yang
Homework #1 (v170410)
(Deadline: 11:59PM PDT, April 21, 2017)
Solution
Name (Last, First):
Student Id #:
INSTRUCTIONS
This homework is to be done individually. You may use any tools or refer to published p
UCLA | EEM16/CSM51A | Spring 2017
Prof. C.K. Yang
Verilog Getting Started (v170428)
1. Software: There are many different ways to run this. Details for each is provided in different sections
below.
o Web interface: https:/www.edaplayground.com/
o (Optiona
EE M16: Logic Design of Digital Systems
Fall 2016
Discussion #7Solutions
Instructor: Prof. Danijela Cabric
Scribe: Ghaith Hattab
Problem 1. The canonical form takes the format shown below.
)(
Input
Combinational
Logic
(+ 1)
NS
State
register
)(
PS
)(
Out
EE M16: Logic Design of Digital Systems
Fall 2016
Assignment #5 Solutions
Instructor: Prof. Danijela Cabric
Scribe: Ghaith Hattab
Exercise A1 (Timing Constraints). Note that it is assumed here that the inputs are synced with the same
clock.
The clock cycl
EE M16: Logic Design of Digital Systems
Fall 2016
Assignment #5 due Monday, November 21, 2016
Instructor: Prof. Danijela Cabric
Scribe: Ghaith Hattab
Exercise A1 (Timing Constraints). Consider the following schematic below.
30
30
20
20
20
10
D
30
;
Q
30
2
EE M16: Logic Design of Digital Systems
Fall 2016
Assignment #4 due Wednesday, November 9, 2016
Instructor: Prof. Danijela Cabric
Scribe: Ghaith Hattab
Exercise A1 (State diagram). Give a complete state diagram of the following machine which implements th