x1
Y1
y1
Y0
x0
y0
x0
x0
phase 1
phase 2
z
a,b,d
c
c
A/0
C/0
a
b,d
b,d
a
B/1
a
c
D/1
b,c,d
1/0
start
0/0
0/0
0/0
1/0
0
0/0
01
010
1/0
1/0
1/1
0/0
1/0
010101
1/0
0/0
0101
0/0
01010
x
y0
y2
x
y2
y0
x
y1
y0
x
y2
y1
y0
y2
Y1
x
x
y1
y0
x
Y2
y1
y0
Y0
CK
z
Combin
f0
f0
OR
f1
f3
OR
f2
T
f1
f4
F
T
f3
OR
f2
Group 1
AND
f4
F
f5
f6
Group 2
f5
AND
f6
f7
f8
f7
f8
(a) sequential execution graph
(b) group sequential execution graph
(max of 2 operations per group)
Input
a, error
z=1
w=z*z
Y
N
output z
i
2
*
a=6*5
11
inputs
x3
M
x
CK
LD
CLR
S Q
R
CK
x0
LD
CLR
q1
M
x1
q2
M
x2
q3
M
M
q0
Q1
Q0
Q3
Q2
Q1
Ir
Shift
Parallel In/out RSR
LOAD
Q0
Q3
Ir
Shift Right
Shift Left
CK
I3
Q2
I2
I1
I0
IL
b
a
16
16
Load
CK
parallel input
1
parallel input
shift reg.
1
shift reg.
Shift
Shift
CK
CL
c
c
b
(0,0)/p
(0,1)/q
b
a
a
a
a
b
(1,0)/p
c
(1,1)/p
b
c
a/0
a/0
c/0
b/1
A
B
c/1
b/1
c/1
b/1
C
c/1
b/1
c/0
E
b/1
a/0
a/0
D
a/0
a
1/1
a,c
a
c
b,c
2/0
3/1
b
b
b
c
0/0
a
c
b
4/0
a
0
0
1
0
1
15
1
0
1
2
0
14
0
1
1
1
0
1
3
1
0
13
0
0
0
1
1
1
4
0
12
1
0
0
5
1
0
1
a
b
c
a
b
d
a
c
d
b
c
d
a
b
e
a
c
e
a
d
e
b
c
e
b
d
e
c
d
e
a
b
c
e
a
b
d
e
a
c
d
e
b
c
d
e
f(a,b,c,d,e)
x0
s0
y0
cin
A
s1
x1
y1
cout
0
0
y3
y2
x3
y1
x2
x1
x0
x2
x1
y0
x2
x0
x2
x1
x0
x2
x1
x0
x2
x1
x0
x2
x1
x0
z3
x2
x1
x0
x2
x1
x0
z1
x2
x1
x0
x3
z2
x0
z0
b
c
d
a
b
c
b
c
d
a
c
d
y
b
d
a
d
b
c
a
b
c
y
a
b
d
a
b
c
b
c
d
a
c
d
c
d
e
b
c
e
b
d
e
a
b
e
a
d
e
a
c
e
f
a
b
d
b
c
d
a
c
e
b
c
e
a
b
c
a
c
d
a
b
e
a
d
e
f
b
d
e
c
d
e a
b
c
a e
b
d
e
b
c
d
e
a
c
d
e
a
b
c
d
x0
y0
cin
x0
y0
cin
z0
x0
y0
cin
x1
x0
y0
cin
R
A
B
S
C
T
Z
E
D
X
Y
R
A
B
S
E
T
D
C
Z
x
1
*
x
x
1
NOT gate
xy
*
y
*
AND gate
x1
T2
z1
x0
T1
T3
z0
T4
x1
T2
z1
x0
T1
T3
z0
T4
AND-5
I6
I6
A
B
AND3
AND2
C
OR4
z0
0.084
0.096
A
0.101
0.134
B
0.392
0.462
C
0.475
0.168
z
z0
z0
0.05+0.017L
0.02+0.038L
AND-5
s
V
DD
a
b
c
d
z
a
b
c
d
V
DD
a
b
c
d
z
a
d
b
c
(a) using AND and NOR circuits
V
DD
a b c d
V
DD
z
(b) using complex gate approach
V
DD
x1
x0
z
x1
GATE TIMING
Input
0.58
0.60
0.73
0.85
output
L=1
output
L=2
