313
Chapter 15
Exercise 15.1
Addr Enable Rd Data Rdy t=0 t=65ns 5ns 30ns 50ns 10ns
Figure 15.1: Single memory read - Exercise 15.1
Rdy becomes active at time t = 55 ns. The enable signal may become low at time t = 65 ns. For a sequence of read operations,
37
Chapter 3
Exercise 3.1
December 10, 1998
a logic values Voltage V Positive Logic Negative Logic 1.0 0 1 4.5 1 0 2.0 unde ned unde ned -1.0 unde ned unde ned
b module has the following behavior voltage levels: Positive Logic Negative Logic 0.3 0.3 4.5 4
EE203A Digital System Homework #6
Verilog HDL
1. Design an 8-bit adder and verify the 8-bit adder with some arbitrary input test patterns. (5 points) a) Design a 1-bit half adder module by using gate primitive instances. b) Design a 1-bit full adder modul
EE M16 Fall 2003 Homework Solution #1
2.1 A combinational system has one input x , which represents a decimal digit. The output z is the square of x if x is greater than 4 ; otherwise, the output z is two times x . a. Give a high-level description of the
UCLA
Department of Electrical Engineering
EEM16 Spring 2011
Homework 1
Due April 6th, 2011
(this homework has 5 problems)
1. Number Representation: Find w, x, y, and z
a. (2750)8 = (w)16
b. (3E5F)16 = (x)8
c. (241)5 + (312)7 = (y)9
d. (0.10011)2 = (z)10
2
UCLA
Department of Electrical Engineering
EEM16 Spring 2011
Homework 3
Due April 20, 2011
(This homework contains 6 problems)
Problem 1 Ex 3.9
Problem 2 Ex 3.4
Problem 3 Ex 4.8
Problem 4 Ex 4.13
Problem 5
Use a * gate that implements the following logic:
UCLA
Department of Electrical Engineering
EEM16 Spring 2011
Homework 4
Due April 25, 2011
(This homework contains 6 problems)
Problem 1 Ex 7.1
Problem 2 Ex 7.6
Problem 3 Ex 7.10
Problem 4 Ex 7.18
Problem 5 Ex 7.21
Problem 6 Ex 7.23
New! Problem 7 Ex 8.27
UCLA
Department of Electrical Engineering
EEM16 Spring 2011
Homework 6
Due May 16, 2011
(This homework contains 5 problems)
Problem 1
Using four-bit binary adders and NAND gates only, design the following:
a) Design a one-digit decimal adder in the BCD co
UCLA
Department of Electrical Engineering
EEM16 Spring 2011
Homework 7
Due May 25, 2011
(This homework contains 4 problems)
Problem 1
Design a bit-serial arithmetic unit (i.e. input x and y are fed in parallel 16-bits,
output z comes out in parallel 16-bi
UCLA
Department of Electrical Engineering
EEM16 Spring 2011
Homework 2
Due April 13, 2011
(This homework contains 5 problems)
Problem 1
a. Show algebraically that the following expressions are equivalent
(
)
(
)
(
b. Give the product of maxterms for
)
(
)
SOLUTIONS TO EXERCISES
for Milo D. Ercegovac, Toms Lang and Jaime H. Moreno s a Wiley & Sons, New York, 1999
INTRODUCTION TO DIGITAL SYSTEMS
prepared by
Alexandre F. Tenca, Toms Lang, Milo D. Ercegovac, and J.H. Moreno a s with the help of L. Alkalai, E.
41
Chapter 4
Exercise 4.1
a gure 4.17a presents a valid gate network b the network in gure 4.17b is not valid since: the load factor L imposed to one of the 2-input AND gates exceeds the fan-out factor F of this gate; two outputs are connected together. c
EEM16- HW#4 Ch. 7: 3, 5, 9, 15, 19 Note: for 7.19, just do a minimum number of states approach. You dont need to use the minimization procedure use your knowledge to design the state machine with the least number of states possible. Ch. 8: 5, 6, 17, 27 No
EE M16 Homework #2
Exercise 4.4 For the following tabular description of a network, give its graphical description and determine whether the network is valid. If not valid, make the modifications in the description so that it is valid. From R S A A2 T X Z
289
Chapter 14
Exercise 14.1
The design of the 2-read/1-write register le can be implemented with registers with 2 tristate outputs (A and B ), as shown in Figure 14.1. We call these registers: RF Registers. Besides the two tristate outputs, they have one
267
Chapter 13
Exercise 13.1
Graphs for cases (a) and (b) are shown in Figure 13.1.
f0 OR f1 f3 OR f2 T f1 f2 AND T F f3 f5 f5 AND f7 f6 f8 f7 f4 F f6 Group 2 OR Group 1 f0
f4
f8 (a) sequential execution graph (b) group sequential execution graph (max of
249
Chapter 12
The controller has 6 states, and we are going to use the one- ip- op per state appoach for the design. The inputs are: Input condition GO A DIST > 10 B (DIST 10) and (COUNT = 3) C (DIST 10) and (COUNT 6= 3) Calling the inputs of the ip ops
215
Chapter 11
The register requires the load (LD), clear (CLR), and data inputs that are not available in the SR ip op. We need to design a combinational network to generate the correct SR inputs as shown in the next table: x LD CLR S R 00 0 00 00 1 01 0
189
Chapter 10
Comparison of FA implementations (a) using a two-level network (Fig. 10.3(a) of the textbook) the critical path for the circuit has 3 gates. The path connects the input xi (or yi or ci ) and output zi . The propagation delay of this path is
119
Chapter 8
problem. a The minimum delay of the combinational network tp considered in this problem is obtained by the following equation tp + 2ns 5ns ! tp 3ns b If the delay of the combinational network can decrease by 30 and the latch delay can decrea
99
Chapter 7
Exercise 7.1
Input:
Output: Function:
xt 2 fa; b; cg z t 2 fp; qg
z t = q if number of a's in x0; t , 1 is even and number of b's is odd. p otherwise
State:
st = sa t; sb t sat = number of a's mod 2 sb t = number of b's mod 2
Initial state:
s
85
Chapter 6
Exercise 6.1 From Exercise 5.11, we know that the single-error detector for a 2-out-of-5 code a; b; c; d; e is implemented by the expression: E a; b; c; d; e = abc + abd + acd + bcd + abe + ace + ade + bce + bde + cde + a b c e + a b d e + ac
55
Chapter 5
Exercise 5.1
z x 0101 0100 y x
z -011 -001 y
f1
Exercise 5.2
f0
a the K-map for E x; y; z =
P m1; 5; 7 is:
z x 0100 0110 y
0
bE w; x; y; z = w x y + y z + xz
0 0 0
z 0 1 1 0 1 1 1 1 1 0 0 0 y
Exercise 5.3
w
1 1 1 0
x
a E w; x; y; z = M 1; 3;
UCLA
Department of Electrical Engineering
EEM16 Spring 2011
Homework 5
Due May 9, 2011
(This homework contains 4 problems)
Problem 1
Using a three-input binary decoder and an eight-input binary encoder, implement a
code converter from three-bit binary cod