HW 2
Due September 11th 2015 10 AM
Please refer to Digital Design With an Introduction to the Verilog HDL by Mano and
Ciletti (5th edition) for the following problem set
1.36, 2.4, 2.7 (Draw logic diagrams for the simplified expressions only), 2.9, 2.12,

HW 4
Due February 12th 2016 by 11AM
Please refer to Digital Design With an Introduction to the Verilog HDL by Mano and
Ciletti (5th edition) for the following problem set
4.4 (include schematic), 4.5 (include schematic), 4.7 (the binary output should be t

HW 2
Due January 29th 2016 11 AM
Please refer to Digital Design With an Introduction to the Verilog HDL by Mano and
Ciletti (5th edition) for the following problem set
1.36, 2.4, 2.7 (Draw logic diagrams for the simplified expressions only), 2.9, 2.12, 2.

HW 1
Due January 20th 2016 by 11 A.M
Please refer to Digital Design With an Introduction to the Verilog HDL by Mano and
Ciletti (5th edition) for the following problem set
1.2, 1.3 (b and d), 1.4, 1.9
6. Convert the following twos complement binary number

HW 5
Due February 19th 2016 by 11 A.M
1) Using half adders and/or full adders as building blocks, design
a) A 4-bit incrementer (a circuit that adds one to a 4-bit number)
b) A 4-bit decrementer (a circuit that subtracts 1 from a 4-bit number)
2) Design a

HW 3
Due February 8th 2016 by 11 AM
Please refer to Digital Design With an Introduction to the Verilog HDL by Mano and
Ciletti (5th edition) for the following problem set
3.2 (a, c, e), 3.3(a, d), 3.5(a, c), 3.6(b, d), 3.12 (Provide simplified expressions