1. True or False Questions
For each of the following statements, state T for true or F for false. No explanation necessary. A
statement is false if any part of the statement is wrong. (10 pts in total
cfw_ .- 3 LI. ,-
Name; 3 3i 1 3 1" V" is
5.
Arizona State University
EEE 335 - Final Practice Questions
Spring 2016 ONLINE Name:
* Digital Circuits *
1. (40 pts) For the circuit below, you are giv
Home Work (30 points)
EEE 333
Finite State Machine
Design Traffic Lights
It is often useful to be able to sequence through an arbitrary number of states, staying in each state an
arbitrary amount of t
EEE 335 Midterm Exam 2
Fall 2015
Exam Time: 70 minutes
Show your work to receive any partial credit. State all of your assumptions.
Print legibly! Circle your final answer.
1 Double-sided 8.5x11 is al
Name:
Date 10/24/2016
EEE 335 Laboratory 2 Template
2016 Fall B
General Rules:
All reports need to be saved as PDF format.
If you directly import cadence plots into your presentation, they must have c
Problem 4: Small Signal Analysis
(35 points)
(a = 10pts, b = 15pts, c = 5pts, d = 5pts)
Consider the circuit of Fig. 4A, where Rout is the circuits output resistance. Assume that both transistors
are
Arizona State University
EEE 335: Analog and Digital Circuits
Section 0: Admin
Shimeng Yu
Assistant Professor of Electrical Engineering
and Computer Engineering
[email protected]
http:/faculty.engineer
Keg
Exam #1 Spring 16
EEE 335 March 1,2016
Closed book, notes, two 8.5 x 11 crib sheet and calculator are allowed. Show all
work and include units for all numerical answers. State all assumptions and
EEE 335 Midterm Exam 1
Fall 2015
Exam Time: 70 minutes
Show your work to receive any partial credit. State all of your assumptions.
Print legibly! Circle your final numerical answer.
1 Double-sided 8.
EEE335 Analog and Digital Circuits Fall 2013
Lab # 4: Design and Analysis of Common Source Amplifier with Active Load
Preface to Lab #4
1. Please follow the instructions carefully and hopefully youll
EEE335 Analog and Digital Circuits Fall 2013
Lab #2
Inverter Simulation (contd Lab 1)
Objective: The objective of this lab is to get more familiar with Cadence and perform
inverter simulation based on
EEE 335 Midterm Exam 1
Fall 2015
Exam Time: 70 minutes
Show your work to receive any partial credit. State all of your assumptions.
Print legibly! Circle your final numerical answer.
1 Double-sided 8.
EEE335 Analog and Digital Circuits Fall 2013
Lab # 5: The design of a differential amplifier with passive loads,
using ideal and non ideal current sources
Learning Goal:
In lab is youll become familia
EEE335 Analog and Digital Circuits Fall 2013
Lab #3
Design and Analysis of CMOS Gates
Objective: The objective of this lab is to design and develop a library of 3 basic gates. In this lab youll
design
Arizona State University
EEE 335: Analog and Digital Circuits
Section 1: MOSFET I-V Model
Shimeng Yu
Assistant Professor of Electrical Engineering
and Computer Engineering
[email protected]
http:/facul
Arizona State University
EEE 335: Analog and Digital Circuits
Section 2: Inverter
Shimeng Yu
Assistant Professor of Electrical Engineering
and Computer Engineering
[email protected]
http:/faculty.engin
Arizona State University
EEE 335: Analog and Digital Circuits
Section 5: Memory Circuits
Shimeng Yu
Assistant Professor of Electrical Engineering
and Computer Engineering
[email protected]
http:/facult
Arizona State University
EEE 335: Analog and Digital Circuits
Section 3: Combinational Logic Gates
Shimeng Yu
Assistant Professor of Electrical Engineering
and Computer Engineering
[email protected]
ht
EEE 335 2016 Spring
HW #3
February 9, at the end of the lecture
The problem sets are selected from the textbook A.S. Sedra and K.C. Smith, Microelectronic
Circuits, 6th Edition, Oxford University Pres
EEE 335 2016 Spring
HW #2
Due February 2, at the end of the lecture
The problem sets are selected from the textbook A.S. Sedra and K.C. Smith, Microelectronic
Circuits, 6th Edition, Oxford University
Arizona State University
EEE 335: Analog and Digital Circuits
Section 4: Sequential Logic Circuits
Shimeng Yu
Assistant Professor of Electrical Engineering
and Computer Engineering
[email protected]
ht
EEE 335 Quiz 4
Name:
ASU ID:
For each of the following statements, state T for true or F for false. No explanation
necessary.
Statement
T or F?
(1) The Cgd of a common-source amplifier introduces a ze
EEE 335 Quiz 3
Name:
ASU ID:
For each of the following statements, state T for true or F for false. No explanation
necessary.
Statement
(1) If adding a series resistance to the source of a common-sour
EEE 335 Quiz 2
Name:
ASU ID:
For each of the following statements, state T for true or F for false. No explanation
necessary.
Statement
(1) A CMOS inverter is driving a load capacitor, if the W/L of C