CHAPTER
5
THE CMOS INVERTER
Quantification of integrity, performance, and energy metrics of an inverter
Optimization of an inverter design
5.1
Exercises and Design Problems
5.4.2
5.2
The Static CMOS Inverter An Intuitive
Perspective
Propagation Delay: Fir
EEE 425/591, ASU
Fall 2012, Yu (Kevin) Cao
Homework #5
Due Thursday, November 1st, 10:30am, submitted to me in class.
The objective of this homework is to practice (1) logical efforts, and (2) pass-gate logic design.
For the problems in the homework, assu
EEE 425/591, ASU
Fall 2012, Yu (Kevin) Cao
Homework #6
Due Tuesday, November 13rd, 10:30am, submitted to me in class.
The objective of this homework is to exercise the design of dynamic logic.
Logic styles and power
In this problem, you need to implement
EEE 425/591, ASU
Fall 2012, Yu (Kevin) Cao
Homework #7
Timing in Latch Design
a. For setup time, use the falling edge; for the hold time, use the rising edge of the clock.
b.
c.
To make sure that the output does not see the load, we can put a buffer in be
EEE 425/591, ASU
Fall 2012, Yu (Kevin) Cao
Homework #7
Due Thursday, November 27th, 10:30am, submitted to me in class.
The objective of this homework is to test the design of sequential circuits and understand the
timing issues. Please only answer the Que
EEE 425/591, ASU
Fall 2012, Yu (Kevin) Cao
Homework #8
Due Tuesday, December 4th, 10:30am, submitted to me in class.
The objective of this homework is to go over the design of sequential circuits and related
concepts of timing.
Timing of sequential circui
EEE 425/591, ASU
Fall 2015, Yu (Kevin) Cao
Lab #1
Due Friday, September 18th, 6:00pm, submitted to Assignment at Blackboard.
Submission: Prepare a concise report (< 5 pages) with important results only. You dont have to
include the entire set of your circ
EEE 425/591, ASU
Fall 2015, Yu (Kevin) Cao
Lab #2
Due Wednesday, October 14th, 10:00pm, submitted to Assignment at Blackboard.
Submission: Prepare a concise report (< 5 pages) with important results only. You dont have to
include the entire set of your ci
EEE 425/591, ASU
Fall 2012, Yu (Kevin) Cao
Homework #6
Logic styles and power
X1
X
F
(a)
F
X1
X2
Y1
Z
F
(b)
X2
Y2
(c)
For the static implementation: the probability (P) of power consumption = P(01)=P(0)P(1).
Therefore, in (a):
Node X: P(X: 01) = 0.56 (1-0
EEE 425/591, ASU
Fall 2012, Yu (Kevin) Cao
Homework #1
Due Tuesday, September 11th, 10:30am, submitted to me in class.
The objective of this homework is to practice (1) the construction of digital logic in CMOS
technology, and (2) the basic concept of tim
chapter7-ex.fm Page 1 Wednesday, October 29, 2003 11:52 PM
1
Chapter 7 Problem Set
Chapter 7 PROBLEMS
1. [M, None, 7.4] Figure 1 shows a practical implementation of a pulse register. Clock Clk is ideal with 50% duty cycle.
V DD
Q
X
Q
D Clk d
Clk
Figure 0.
1
Chapter 10 Problem Set
Chapter 10 SOLUTIONS
1. [C, None, 9.2] For the circuit in Figure 0.1, assume a unit delay through the Register and Logic blocks (i.e., tR = tL = 1). Assume that the registers, which are positive edge-triggered, have a set-up time
1
Chapter 6 Problem Set
Chapter 6
PROBLEMS
1.
[E, None, 4.2] Implement the equation X = (A + B) (C + D + E) + F) G using complementary CMOS. Size the devices so that the output resistance is the same as that of an inverter
with an NMOS W/L = 2 and PMOS W/
Cadence Help Session
Ihavenoclueasto
whatImdoing!
CADENCELAB:GWC273
LabHours:
Monday:
Tuesday&Thursday:
Tuesday & Thursday:
Wednesday
Friday:
Saturday,Sunday:
S
d S d
12noonto9pm
8amto10pm
8 am to 10 pm
11.30amto10pm
8amto5.30pm
CLOSED
*Pleasemakesureyou
EEE 425/591, ASU
Fall 2012, Yu (Kevin) Cao
Homework #3
Due Tuesday, October 9th, 10:30am, submitted to me in class.
The objective of this homework is to (1) practice the design of an inverter, and (2) design static
logic circuits.
1. Additional question f
EEE 425/591, ASU
Fall 2012, Yu (Kevin) Cao
Homework #3
1. Additional question for Prob. 3 in Sample Midterm 01 (MOS inverter).
To solve VOL: INMOS (in the linear mode) = IL. Thus, for Load A: VOL = 0.5V; for Load B: VOL
= 0.76V;
For VOH, since Vin = 0, IN
EEE 425/591, ASU
Fall 2012, Yu (Kevin) Cao
Homework #4
Due Tuesday, October 23rd, 10:30am, submitted to me in class.
The objective of this homework is to exercise the design of static CMOS logic. For the problems
in the homework, assume the mobility of a
EEE 425/591, ASU
Fall 2012, Yu (Kevin) Cao
Homework #2
Due Thursday, September 25th, 10:30am, submitted to me in class.
The objective of this homework is to practice (1) the basic knowledge of circuit layout, and (2)
the characteristics of transistor and