chapter7-ex.fm Page 1 Wednesday, October 29, 2003 11:52 PM
1
Chapter 7 Problem Set
Chapter 7 PROBLEMS
1. [M, None, 7.4] Figure 1 shows a practical implementation of a pulse register. Clock Clk is ideal with 50% duty cycle.
V DD
Q
X
Q
D Clk d
Clk
Figure 0.
EEE EDS/5:91
Test 2 .
' April 29: 2015
cfw_al Implement the function FHABCD using Domino logic. Stack no more than 3 transistors cfw_10
points.
cfw_b Inverters are kept at minimum size. Site the Domino transistors and calculate the worst case
dela
Q3. A datapath is given in Figure 2. For this datapath, the minimum and maximum delays are
given in Table 1. Set-up and hold times are both 50ps.
(a) Determine the maximum clock frequency assuming no jitter and skew between clocks (10
points).
(b) For fcl
Lab 4 & 5
Design and Testing
Lab 4&5 Goal
Design an 8 bit modulo adder with minimum EDP and Size
Delay => Clock Period
Energy => Measured from Testbench
Size => Taken from the layout
Free to use any design
Full Adder and D Flip Flop
A
S
B
Cout
Cin
x8
EEE 425/591
Homework #6
Due April 6th
Use SPICE simulations to answer the following questions. Technology: 32nm technology
used in the lab.
Question 1. (50 points)
Figure 1 shows a CMOS latch design. In the inverter, the NMOS width WN=630nm and
(WP/WN)=1.
EEE 425/591 SP 2015 Test 1 NAME:
EEE 425/591
Digital Systems and Circuits
Spring 2015
Test 1
March 2nd, 2015
Use the values in Table I unless otherwise specified.
Table I: Transistor parameters EEE 425/591 SP 2015 Test 1 NAME:
Q1. For the logic function
EEE 425/591
SP 2016
Homework #5
Due March 30
Question 1. (30 points) For the dynamic logic circuit in Figure 1, size the transistors such that an equal
resistance to a minimum sized NMOS transistor is obtained through each charge/discharge path.
Determine
EEE 425/591
Digital Systems and Circuits
Spring 2016
Due Feb 8th, in class
Homework #2
Use the values in Table I unless otherwise specified.
Table I: Transistor parameters
2
2
= 220
= = 0.25
= 560
= 9
= 0.6
= 0.7
Vdd = 2.5V
= = 0.4
2
= 0.4
= 1.7
EEE 425/591 Spring 2016 Lab 3
Due Friday, March 4th, at midnight. Submit on Blackboard.
Submission: Prepare a concise report (<5 pages) with key steps to find the answer and important
results. Please include layout view with DRC and LVS pass screenshots,
EEE 425/591
Digital Systems and Circuits Spring 2016
Homework #4 Solutions
Problem 1 (60 pts):
Q1. A logic circuit is given in Figure 1. For this technology, the minimum sized inverter has 3fF
of input capacitance.
(a) Determine the delay from the input t
EEE 425/591: Digital Systems and Circuits
CMOS Technology
Example:What is the truth table?
Under what conditions is X zero?
A=C=1
B=D=1
A=S=D=1
B=S=C=1
EEE425/591, ASU
Example: Logic Construction
Implement
Using 2-input standard logic gates (NAND,
NOR) a
EEE 425/591: Digital Systems and Circuits
Design Metrics and Logic
Gate Basics
NMOS and PMOS
N-Type MOSFET (NMOS)
te
a
G
p- substrate
p+
n+
Bulk
Source
L
D
W
n+
Drain
Oxide
G
D
D
B G
G
S
S
S
S
S
S
P-Type MOSFET (PMOS)
te
Ga
n+
p+
Source
N-well
EEE425/591,
EEE 425/591, ASU
Fall 2015, Yu (Kevin) Cao
Lab #2
Due Wednesday, October 14th, 10:00pm, submitted to Assignment at Blackboard.
Submission: Prepare a concise report (< 5 pages) with important results only. You dont have to
include the entire set of your ci
EEE 425/591, ASU
Fall 2015, Yu (Kevin) Cao
Lab #1
Due Friday, September 18th, 6:00pm, submitted to Assignment at Blackboard.
Submission: Prepare a concise report (< 5 pages) with important results only. You dont have to
include the entire set of your circ
EEE 425/591, ASU
Homework #3
The objective of this homework is to practice (1) logical efforts, and (2) pass-gate logic design.
For the problems in the homework, assume the mobility of a NMOS transistor = 2x that of a
PMOS transistor.
1. Logical efforts
C
EEE 425/591: Digital Systems and Circuits
MOS Transistors
A Model for Hand Analysis
Threshold voltage (Vth)
Vth Vth0
2 B Vsb
2 B
Linear: Vds < (Vgs Vth)
Vds2
W
I ds Cox Vgs Vth Vds
L
2
Saturation: Vds > (Vgs Vth)
1
W
I ds Cox
2
L
ox
Cox
tox
2
EEE 425/591: Digital Systems and Circuits
MOS Transistors
Outline
Threshold voltage (Vth)
Body effect
Extraction of Vth
Current-voltage relations (IV)
Linear and saturation regions
Channel length modulation
Other advanced effects
Subthreshold regi
EEE 425/591: Digital Systems and Circuits
Inverter Design
CMOS Inverter
VDD
NMOS off
PMOS linear
Vout
IP
Vin
2.5 1
NMOS saturation
2 PMOS linear
Vout
IN
3
1.25
IN = IP
0
0
NMOS: Vgs=Vin, Vds=Vout
PMOS: Vgs=Vin-VDD, Vds=Vout-VDD
NMOS saturation
PMOS satu
EEE 425/591: Digital Systems and Circuits
Layout and Rules
NOR2
VDD
VDD
A
NOT(A+B)
B
A
B
GND
GND
NOT(A+B)
Stick Diagrams
Introduced by Mead & Conway
in the 80s
Every line of a conduction
material layer is represented
by a line of a distinct color
nFET a
EEE 425/591: Digital Systems and Circuits
MOS Capacitances
MOS Transistor Capacitances
The time required to charge and discharge capacitances is the main
component of delay in a CMOS circuit
Channel capacitances
Linear
Depletion regions of the reverse-bia
EEE 425/591: Digital Systems and Circuits
L-7: Inverter Design
Summary
Region
CGB
CGS
CGD
Cut-off
C0xWL
C0W
C0W
Linear
0
C0xWL/2+C0W
C0xWL/2+C0W
Sat
0
(2/3)C0xWL+C0W
C0W
Csb
C j 0 SB
Vsb
1
0
Cdb
m
EEE425/591, ASU
D
CGD
CDB
CGB
C j 0 DB
Vdb
1
0
C
EEE 425/591: Digital Systems and Circuits
L-2: Design Metrics and
Logic Gate Basics
Challenges in Future VLSI
Microscopic Problems
Ultra-high speed design
Interconnect
Noise, Crosstalk
Reliability and
manufacturability
Power Dissipation
Clock distri
EEE 425/591: Digital Systems and Circuits
L-1: Introduction and
VLSI Trends
Basic Information
Instructor: Sule Ozev, ISTB4 - 565, [email protected]
Office hours: TBD
Textbook:
Digital Integrated Circuits: A Design Perspective, by Jan M.
Rabaey, et al.
EEE 425/591
Digital Systems and Circuits Spring 2016
Homework #5 Solutions
Problem 1 (30 pts):
For the dynamic logic circuit in Figure 1, size
the transistors such that an equal resistance to
a minimum sized NMOS transistor is
obtained through each charge
EEE 425
Homework #4
Due Monday March 14
Q1. A logic circuit is given in Figure 1. For this technology, the minimum sized inverter has 3fF of
input capacitance.
(a) Determine the delay from the input to X, Y, and Z assuming all gates are minimum sized.
(b)
EEE 425/591
Homework 7
Question 1. Figure 1 shows a datapath, with timing information in Table 1. Min/max delays through each
component is the same. (50points)
(a) Determine the minimum clock period with no jitter and skew.
(b) Determine the following max
EEE 425/591, ASU
Fall 2012, Yu (Kevin) Cao
Homework #5
Due Thursday, November 1st, 10:30am, submitted to me in class.
The objective of this homework is to practice (1) logical efforts, and (2) pass-gate logic design.
For the problems in the homework, assu