Principles Of
Digital Design
Homework 8: Shift, Decode, and Encode
Shifters/Rotators
Decoders
Encoders
5-bit Shifter/Rotator
1. Lets build a 5-bit shifter/rotator (similar to the 4-bit one
we built in class). We have chosen a few values for you;
complete
Principles Of
Digital Design
Homework 14: Shift, Decode, and Encode
Shifters/Rotators
Basic Decoders
Basic Encoders
5-bit Shifter/Rotator
Lets
build a 5-bit shifter/rotator (similar to the 4-bit one
we built in class). We have chosen a few values for you
Principles Of
Digital Design
Homework 9: RTL Combinatorial
Components
4-to-9 Decoder
16-to-4 Encoder
4-to-9 Decoder
1. Complete the design for the 4-to-9 decoder we started
in class. You can continue using the 1-to-2 decoders, or
you can rebuild it using
Introduction to Digital Logic
EECS/CSE 31L
Assignment 5
EECS Department
Henry Samueli School of Engineering
University of California, Irvine
February, 24, 2015
No submission is required for this assignment and it is not graded.
1
RAM Design
The goal of th
EECS 31L:
Introduction to Digital Design Lab
Lecture 6
Pooria M.Yaghini
The Henry Samueli School of Engineering
Electrical Engineering and Computer Science
University of California, Irvine
Lecture 6: Outline
Processor Design Basics
EECS 31L: Introduction
EECS 31L:
Introduction to Digital Design Lab
Lecture 2
Pooria M.Yaghini
The Henry Samueli School of Engineering
Electrical Engineering and Computer Science
University of California, Irvine
Lecture 2: Overview
VHDL Code Structure
Port Types
Data Object Typ
Principles Of
Digital Design
Homework 22: RTL Design
Absolute Difference (Given Datapath)
Absolute Difference with Fixed Datapath
On the following slides, Generate the control signals for the
given datapath to perform the following algorithm. All
register
EECS 31L:
Introduction to Digital Design Lab
Lecture 3
Pooria M.Yaghini
The Henry Samueli School of Engineering
Electrical Engineering and Computer Science
University of California, Irvine
Lecture 3: Outline
Testbench Development
FOR / GENERATE Loop
Data
EECS 31L:
Introduction to Digital Design Lab
Lecture 4
Pooria M.Yaghini
The Henry Samueli School of Engineering
Electrical Engineering and Computer Science
University of California, Irvine
Lecture 4: Quiz
Quiz 1 Combinational Circuit Modeling
EECS 31L: In
EECS 31L:
Introduction to Digital Design Lab
Lecture 1
Pooria M.Yaghini
The Henry Samueli School of Engineering
Electrical Engineering and Computer Science
University of California, Irvine
Lecture 1: Overview
Course Administration
Course outline and over
EECS 31L:
Introduction to Digital Design Lab
Lecture 7
Pooria M.Yaghini
The Henry Samueli School of Engineering
Electrical Engineering and Computer Science
University of California, Irvine
Lecture 7: Outline
Finite State Machine
EECS 31L: Introduction to
EECS 31L:
Introduction to Digital Design Lab
Lecture 5
Pooria M.Yaghini
The Henry Samueli School of Engineering
Electrical Engineering and Computer Science
University of California, Irvine
Lecture 5: Outline
GENERIC example
VHDL Subprograms: FUNCTION, PRO
EECS 31L
Final Project
Winter 2015
University of California, Irvine
Submission notes
In this assignment you finish the project of this course.
Have your VHDL files compressed and upload it with this format :
FinalProject_student_id_cpu.rar
Your explanatio
Introduction to Digital Logic
EECS/CSE 31L
Assignment 4
EECS Department
Henry Samueli School of Engineering
University of California, Irvine
February, 9, 2015
Due on Monday 2/23/2015 5:00pm. Note: this is a two-week assignment
1
Design and implementation
Introduction to Digital Logic
EECS/CSE 31L
Assignment 1
University of California, Irvine
January, 12, 2015
Due on Monday 1/26/2015 5:00pm. Note: this is a two-week assignment
Lab assignments in this course are dened in a way to employ dierent aspects of y
Principles Of
Digital Design
Homework 15: Latches
Trying to remember ;)
SR Latch Processing
1. For this exercise, process an SR latch w/ the design
from the lecture slides (2 NOR gate version). Process the
circuit on paper (take a picture of it) or in a d
Introduction to Digital Logic
EECS/CSE 31L
Assignment 3
EECS Department
Henry Samueli School of Engineering
University of California, Irvine
February, 2, 2015
Due on Monday 2/9/2015 5:00pm. Note: this is a one-week assignment
1
Implementing a 32-bit ALU [
CS 171 Introduction to Artificial Intelligence
Programming Assignment: Wumpus World AI
Abdullah Younis
[email protected]
June 25, 2016
C+
* If ou are i a Wi do s E iro e t ou ill eed to appe d .e e to the e d of a
executable. For example, i stead of ./Pract
Introduction to Digital Logic
EECS/CSE 31L
Assignment 2
EECS Department
Henry Samueli School of Engineering
University of California, Irvine
January, 26, 2015
Due on Monday 2/2/2015 5:00pm. Note: this is a one-week assignment
1
Implementing a 1-bit ALU [1
Principles Of
Digital Design
Homework 1: Numbers!
(and a little bit of Arithmetic)
Binary to Decimal Conversion
Decimal to Binary Conversion
Some Unsigned Binary Arithmetic
Binary and Decimal Conversion
1. Complete the following table:
Unsigned Binary 01
Principles Of
Digital Design
Homework 2: Arithmetic
Twos Complement Arithmetic
No Sign-Magnitude because it Sucks.
Floating Point next time.
Binary Arithmetic: Twos Complement
3. Subtract the following 7-bit twos complement numbers:
8 - 15
-40 - 33
+/- 32
Principles Of
Digital Design
Homework 18: Flip-flops and Latches
Timing Diagrams
Latch and Flip-flop Comparison
1. Compare the behavior of D latch and D flip-flop devices
by completing the timing diagram in the figure below.
Assume each device initially s
Principles Of
Digital Design
HW 19:
FSM Design Analysis
FSM Design Analysis
FSM Design Analysis
1. Problem: This circuit does something. We have to
figure out what. Derive the next-state equations, state
table, and state diagram for the sequential circuit
Principles Of
Digital Design
Homework 20: FSMs
State Minimization
FSM Design
1. Draw the FSM for the table shown
S0
S1
S2
S3
S4
S5
S6
S7
Answer:
Flip-Flops and FSM Design
PRESENT STATE
2
NEXT STATE
/Output
x=0
x=1
S0/1
S4/0
S0/0
S4/0
S1/0
S5/0
S1/0
S5/0
S
Principles Of
Digital Design
Homework 5: Boolean Functions+*2
Boolean Functions
Boolean Expression to Canonical Form
Canonical Form to Standard Form
Boolean Function Complement
1. Practice simplifying! Reduce to sum-of-product form
(refer to the lecture v
Principles Of
Digital Design
Homework 3: Boolean Algebra
Axioms & Theorems
Theorem Proving
1. In class, we proved Theorem 3a via truth table. Please
go ahead and prove Theorem 3b via truth table. You can
add/remove any columns you need. Below is just a
te
Principles Of
Digital Design
Homework 16: Flip-flops
Flip-flops vs Latches
Reading / Videos
This homework is intentionally short. I would like you to
first watch the Flip-Flop lecture & example videos before
continuing the homework. Alternatively, you can
Principles Of
Digital Design
Homework 23: RTL Storage Components
Up/Down Counter
Pattern Recognizer (FSM Stuff)
Timer Counter
1. We need to run a circuit that needs a clock frequency of 1MHz with a
75% duty cycle (i.e. value of clock is 1 for 75% of its p
Principles Of
Digital Design
Homework 4: Boolean Functions+
Boolean Functions
Boolean Expression to Canonical Form
Canonical Form to Standard Form
Boolean Expression Equivalence
1. Prove the following (show and comment each step):
x + xy = x + y
Answer: